IMX6 Power up timing and latching

jparrish88 — Thu, 13 Aug 2015 15:50:09 GMT

Hello All,

Can someone help me figure out the timing spec with relationship to the external pin that configures the processor at reset? I would like to know exactly when the configuration pin are latched into the imx6 processor with respect to reset and the clock signals. I have boards that are not being configured properly at power-up..The User guid has a large section (7.2.1) devoted to power sequenceing, but it does not show signal to latch timing. I do not see any time signal referencing the configuration bit (see Table 8-3 in the reference manual) to any signal with respect to latching the configuration bits. Are the config bits latched on the rising edge of the reset signal or some other clock signal? When are those bits latched into the processor and what signal latches them?

Re: IMX6 Power up timing and latching

igorpadykov — Fri, 14 Aug 2015 01:27:48 GMT

Hi jparrish88

one can look at comments in attached image from i.MX6SL EVK schematic

spf-27452.pdf p.13

Best regards

igor

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topic IMX6 Power up timing and latching in i.MX Processors

IMX6 Power up timing and latching

Re: IMX6 Power up timing and latching