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    <title>topic Re: i.MX6SDL IPU CSI capability when use both parallel camera port and MIPI-CSI2. in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6SDL-IPU-CSI-capability-when-use-both-parallel-camera-port/m-p/437216#M66988</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt; The i.MX6 S / DL can capture the mentioned inputs.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Would you let me know how did you judge it?&lt;/P&gt;&lt;P&gt;In the mentioned case, 168MHz + 89MHz = 257MHz &amp;gt; 240MHz(max speed of parallel interface), so I guessed i.MX6SDL cannot capture them.&lt;/P&gt;&lt;P&gt;But your reply was it is possible.&lt;/P&gt;&lt;P&gt;Do the input capability of prallel port and MIPI-CSI2 don't effect each other?&lt;/P&gt;&lt;P&gt;In other words, can IPU capture 125MHz (2Gbps, 2 data lane configure) data via MIPI-CSI2 when IPU receives 240MHz data via parallel port?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt; But, also, please take into account memory throughput, since&lt;/P&gt;&lt;P&gt;&amp;gt; memory usually is used by others applications too.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Yes, we think we should evaluate with actual use case.&lt;/P&gt;&lt;P&gt;But at first, we have to judge whether i.MX6SDL satisfies our use case theoretically.&lt;/P&gt;&lt;P&gt;If i.MX6SDL cannot satisfy our use case, we should evaluate i.MX6DQ instead of i.MX6SDL, or we should surrender using i.MX6 series.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Satoshi Shimoda&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 24 Apr 2015 02:31:22 GMT</pubDate>
    <dc:creator>satoshishimoda</dc:creator>
    <dc:date>2015-04-24T02:31:22Z</dc:date>
    <item>
      <title>i.MX6SDL IPU CSI capability when use both parallel camera port and MIPI-CSI2.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6SDL-IPU-CSI-capability-when-use-both-parallel-camera-port/m-p/437214#M66986</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi community,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We have a question about i.MX6SDL IPU CSI capability.&lt;/P&gt;&lt;P&gt;Please see page 2790, 2791 in IMX6SDLRM Rev.1.&lt;/P&gt;&lt;P&gt;There are the CSI capability to input via parallel port or MIPI-CSI2 individually.&lt;/P&gt;&lt;P&gt;Then, how about when use both port (parallel and MIPI-CSI2)?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;For example, how judge whether i.MX6SDL can receive the following input?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Parallel: 1920 x 1080 x 30fps x 1.35 x 2(YUV422 over 8 bit) = 168MHz&lt;/P&gt;&lt;P&gt;MIPI-CSI2: 1280 x 1024 x 30fps x 1.35 x 1.5(RGB888) = 89MHz (1.9Gbps)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Satoshi Shimoda&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 23 Apr 2015 09:58:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6SDL-IPU-CSI-capability-when-use-both-parallel-camera-port/m-p/437214#M66986</guid>
      <dc:creator>satoshishimoda</dc:creator>
      <dc:date>2015-04-23T09:58:40Z</dc:date>
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    <item>
      <title>Re: i.MX6SDL IPU CSI capability when use both parallel camera port and MIPI-CSI2.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6SDL-IPU-CSI-capability-when-use-both-parallel-camera-port/m-p/437215#M66987</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt; The i.MX6 S / DL can capture the mentioned inputs.&lt;BR /&gt;But, also, please take into account memory throughput, since&lt;BR /&gt;memory usually is used by others applications too. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 23 Apr 2015 11:42:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6SDL-IPU-CSI-capability-when-use-both-parallel-camera-port/m-p/437215#M66987</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-04-23T11:42:46Z</dc:date>
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    <item>
      <title>Re: i.MX6SDL IPU CSI capability when use both parallel camera port and MIPI-CSI2.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6SDL-IPU-CSI-capability-when-use-both-parallel-camera-port/m-p/437216#M66988</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt; The i.MX6 S / DL can capture the mentioned inputs.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Would you let me know how did you judge it?&lt;/P&gt;&lt;P&gt;In the mentioned case, 168MHz + 89MHz = 257MHz &amp;gt; 240MHz(max speed of parallel interface), so I guessed i.MX6SDL cannot capture them.&lt;/P&gt;&lt;P&gt;But your reply was it is possible.&lt;/P&gt;&lt;P&gt;Do the input capability of prallel port and MIPI-CSI2 don't effect each other?&lt;/P&gt;&lt;P&gt;In other words, can IPU capture 125MHz (2Gbps, 2 data lane configure) data via MIPI-CSI2 when IPU receives 240MHz data via parallel port?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt; But, also, please take into account memory throughput, since&lt;/P&gt;&lt;P&gt;&amp;gt; memory usually is used by others applications too.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Yes, we think we should evaluate with actual use case.&lt;/P&gt;&lt;P&gt;But at first, we have to judge whether i.MX6SDL satisfies our use case theoretically.&lt;/P&gt;&lt;P&gt;If i.MX6SDL cannot satisfy our use case, we should evaluate i.MX6DQ instead of i.MX6SDL, or we should surrender using i.MX6 series.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Satoshi Shimoda&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 24 Apr 2015 02:31:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6SDL-IPU-CSI-capability-when-use-both-parallel-camera-port/m-p/437216#M66988</guid>
      <dc:creator>satoshishimoda</dc:creator>
      <dc:date>2015-04-24T02:31:22Z</dc:date>
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    <item>
      <title>Re: i.MX6SDL IPU CSI capability when use both parallel camera port and MIPI-CSI2.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6SDL-IPU-CSI-capability-when-use-both-parallel-camera-port/m-p/437217#M66989</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;nbsp; The mentioned restriction of 240 MHz relates to single CSI port of IPU; &lt;BR /&gt;thera are no specifications about total restriction for both CSI ports of single IPU. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards, &lt;/P&gt;&lt;P&gt;Yuri&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 29 Apr 2015 09:52:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6SDL-IPU-CSI-capability-when-use-both-parallel-camera-port/m-p/437217#M66989</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-04-29T09:52:39Z</dc:date>
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