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    <title>topic Re: UART parity and flow control information in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/UART-parity-and-flow-control-information/m-p/435452#M66652</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;Jack,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&lt;BR /&gt; Please look at my comments below.&lt;BR /&gt;1.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; Basically PREN (Parity Enable) and PROE (Parity Odd/Even) bits of &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;UARTx_UCR2 registers allows to control the 9-th bit in UART frame,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;but – alas – it is not possible to predefine the values of this bit as&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;MARK or SPACE.&lt;BR /&gt; Also, in RS-485 mode 9-th bit is supported : it may used to send any&lt;BR /&gt; data (0 /1).&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;2.&lt;BR /&gt; Yes, the UART includes hardware flow control support for request to &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;send (RTS_B) and clear to send (CTS_B) signals. But&amp;nbsp; DTR and DSR&lt;BR /&gt; signals also present.&lt;BR /&gt; &lt;BR /&gt;3.&lt;BR /&gt; From “Universal Asynchronous Receiver/Transmitter (UART) Driver”&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;of "i.MX_6_Linux_Reference_Manual.pdf" : the low-level UART driver has &lt;BR /&gt; XON/XOFF software flow control.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 24 Apr 2015 10:44:30 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2015-04-24T10:44:30Z</dc:date>
    <item>
      <title>UART parity and flow control information</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/UART-parity-and-flow-control-information/m-p/435451#M66651</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi expert,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I want to confirm these information about UART:&lt;/P&gt;&lt;P&gt;1. @IMX6SL platform, UART parity only have ODD/EVEN mode, but not contain MARK and SPACE, is it right? Further more, is there any upgrade for this to support MARK &amp;amp; SPACE?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2. about the flow control, the spec shows that this platform only support RTS/CTS HW flow control.&lt;/P&gt;&lt;P&gt;what is it about DTR/DSR?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;3. how to use SW flow control (XON/XOFF)? &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank You!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BRs,&lt;/P&gt;&lt;P&gt;Jack&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 23 Apr 2015 01:01:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/UART-parity-and-flow-control-information/m-p/435451#M66651</guid>
      <dc:creator>jacklu</dc:creator>
      <dc:date>2015-04-23T01:01:27Z</dc:date>
    </item>
    <item>
      <title>Re: UART parity and flow control information</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/UART-parity-and-flow-control-information/m-p/435452#M66652</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;Jack,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&lt;BR /&gt; Please look at my comments below.&lt;BR /&gt;1.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; Basically PREN (Parity Enable) and PROE (Parity Odd/Even) bits of &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;UARTx_UCR2 registers allows to control the 9-th bit in UART frame,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;but – alas – it is not possible to predefine the values of this bit as&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;MARK or SPACE.&lt;BR /&gt; Also, in RS-485 mode 9-th bit is supported : it may used to send any&lt;BR /&gt; data (0 /1).&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;2.&lt;BR /&gt; Yes, the UART includes hardware flow control support for request to &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;send (RTS_B) and clear to send (CTS_B) signals. But&amp;nbsp; DTR and DSR&lt;BR /&gt; signals also present.&lt;BR /&gt; &lt;BR /&gt;3.&lt;BR /&gt; From “Universal Asynchronous Receiver/Transmitter (UART) Driver”&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;of "i.MX_6_Linux_Reference_Manual.pdf" : the low-level UART driver has &lt;BR /&gt; XON/XOFF software flow control.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 24 Apr 2015 10:44:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/UART-parity-and-flow-control-information/m-p/435452#M66652</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-04-24T10:44:30Z</dc:date>
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