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    <title>topic Re: DMA with FPGA in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/DMA-with-FPGA-removed/m-p/435161#M66585</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; The SDMA controller helps to optimize system performance by offloading&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;the CPU in dynamic data routing with relatively slow channels, such as UART,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;SSI, SPI. The SDMA is not the best solution to achieve maximal throughput.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;The ARM architecture provides more effective tools for it, such as special&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;block transfer instructions LDM / STM or NEON VLD / VST instructions for burst &lt;BR /&gt;transfers.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; I think it would be better to use the PCIe interface for high speed data.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 23 Apr 2015 11:52:46 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2015-04-23T11:52:46Z</dc:date>
    <item>
      <title>DMA with FPGA(removed)</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DMA-with-FPGA-removed/m-p/435160#M66584</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;removed&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 23 Apr 2015 02:07:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DMA-with-FPGA-removed/m-p/435160#M66584</guid>
      <dc:creator>chilwonna</dc:creator>
      <dc:date>2015-04-23T02:07:02Z</dc:date>
    </item>
    <item>
      <title>Re: DMA with FPGA</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DMA-with-FPGA-removed/m-p/435161#M66585</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; The SDMA controller helps to optimize system performance by offloading&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;the CPU in dynamic data routing with relatively slow channels, such as UART,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;SSI, SPI. The SDMA is not the best solution to achieve maximal throughput.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;The ARM architecture provides more effective tools for it, such as special&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;block transfer instructions LDM / STM or NEON VLD / VST instructions for burst &lt;BR /&gt;transfers.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; I think it would be better to use the PCIe interface for high speed data.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 23 Apr 2015 11:52:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DMA-with-FPGA-removed/m-p/435161#M66585</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-04-23T11:52:46Z</dc:date>
    </item>
    <item>
      <title>Re: DMA with FPGA</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DMA-with-FPGA-removed/m-p/435162#M66586</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thank your suggestions.&lt;/P&gt;&lt;P&gt;But, There are several difficulties for PCIe.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I try to lower spec of the camera.&lt;/P&gt;&lt;P&gt;(1.3MP(1280*960), 30fps, dual parallel camera. data/sec = about 75MB)&lt;/P&gt;&lt;P&gt;Is it possible?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Perhaps,&lt;/P&gt;&lt;P&gt;Is CSI able to receive dual parallel camera input?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have one more question.&lt;/P&gt;&lt;P&gt;I thought EIM port instead of old cpu's local bus.&lt;/P&gt;&lt;P&gt;Is this right?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 24 Apr 2015 00:27:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DMA-with-FPGA-removed/m-p/435162#M66586</guid>
      <dc:creator>chilwonna</dc:creator>
      <dc:date>2015-04-24T00:27:01Z</dc:date>
    </item>
    <item>
      <title>Re: DMA with FPGA</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DMA-with-FPGA-removed/m-p/435163#M66587</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Please look at my comments below.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1.&lt;/P&gt;&lt;P&gt; From the following thread &lt;A href="https://community.nxp.com/message/480163"&gt;i.MX6 SDMA performance&lt;/A&gt;&lt;/P&gt;&lt;P&gt;the SDMA performance is estimated as 40 - 60 MB/sec.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;2.&lt;BR /&gt; Up to three cameras may be connected to i.MX6. Please take a look &lt;/P&gt;&lt;P&gt;at Figure 19-1 (CSI2IPU gasket connectivity) of the i.MX6 Reference &lt;BR /&gt;Manual.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf" title="http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf"&gt;http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;3.&lt;BR /&gt;&amp;nbsp; The i.MX6 EIM&amp;nbsp; may be considered as general purpose (SRAM-like) memory &lt;BR /&gt;interface.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 27 Apr 2015 11:20:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DMA-with-FPGA-removed/m-p/435163#M66587</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-04-27T11:20:55Z</dc:date>
    </item>
    <item>
      <title>Re: DMA with FPGA</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DMA-with-FPGA-removed/m-p/435164#M66588</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Your suggestions were very helpful.&lt;/P&gt;&lt;P&gt;Would you like to help me once more?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I changed the concept.&lt;/P&gt;&lt;P&gt;I selected FHD parallel sensor with bayer output.&lt;/P&gt;&lt;P&gt;Camera is two.&lt;/P&gt;&lt;P&gt;Camera will be connected to each CSI0 &amp;amp; CSI1.&lt;/P&gt;&lt;P&gt;I will capture from two camera concurrently. and the first camera input has to display in real time to the parallel LCD.&lt;/P&gt;&lt;P&gt;Is it possible?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 28 Apr 2015 02:47:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DMA-with-FPGA-removed/m-p/435164#M66588</guid>
      <dc:creator>chilwonna</dc:creator>
      <dc:date>2015-04-28T02:47:30Z</dc:date>
    </item>
    <item>
      <title>Re: DMA with FPGA(removed)</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DMA-with-FPGA-removed/m-p/435165#M66589</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-family: Verdana, sans-serif;"&gt;&amp;nbsp; As for two camera support - yes, basically it is possible.&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: Verdana, sans-serif;"&gt;Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: Verdana, sans-serif;"&gt;Yuri.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 26 Nov 2015 02:06:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DMA-with-FPGA-removed/m-p/435165#M66589</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-11-26T02:06:50Z</dc:date>
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