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    <title>topic Re: Bidirectional SPI communication in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Bidirectional-SPI-communication/m-p/175941#M6609</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;In order to use SSP for bidirectional data transfer, I think we have to use SSP without DMA. To do a single transmission should not be difficult but in order to handle it efficiently for multi words transmission using interrupt driven routines will be completely different.&lt;/P&gt;&lt;P&gt;I really like to see examples on accessing the SSP data FIFO directly too. There is very little information about it in the datasheet. I cannot even find out the size of the FIFO!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 23 Jul 2012 03:27:49 GMT</pubDate>
    <dc:creator>Conrad1z</dc:creator>
    <dc:date>2012-07-23T03:27:49Z</dc:date>
    <item>
      <title>Bidirectional SPI communication</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Bidirectional-SPI-communication/m-p/175940#M6608</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The i.MX28 has a single DMA channel for SSP. So, only half-duplex transmission is possible in DMA mode. But "The SPI bus is inherently a full-duplex bidirectional interface" (17.5.1 in the reference manual).&lt;/P&gt;&lt;P&gt;How can I set up a single bidirectional transmission (Write data register -&amp;gt; start transmission -&amp;gt; read data register)? &amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 19 Jul 2012 07:12:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Bidirectional-SPI-communication/m-p/175940#M6608</guid>
      <dc:creator>AndresErni</dc:creator>
      <dc:date>2012-07-19T07:12:45Z</dc:date>
    </item>
    <item>
      <title>Re: Bidirectional SPI communication</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Bidirectional-SPI-communication/m-p/175941#M6609</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;In order to use SSP for bidirectional data transfer, I think we have to use SSP without DMA. To do a single transmission should not be difficult but in order to handle it efficiently for multi words transmission using interrupt driven routines will be completely different.&lt;/P&gt;&lt;P&gt;I really like to see examples on accessing the SSP data FIFO directly too. There is very little information about it in the datasheet. I cannot even find out the size of the FIFO!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 23 Jul 2012 03:27:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Bidirectional-SPI-communication/m-p/175941#M6609</guid>
      <dc:creator>Conrad1z</dc:creator>
      <dc:date>2012-07-23T03:27:49Z</dc:date>
    </item>
    <item>
      <title>Re: Bidirectional SPI communication</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Bidirectional-SPI-communication/m-p/175942#M6610</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Did you make any progress on an i.MX28 full-duplex SPI driver?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;S&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 21 Nov 2012 02:01:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Bidirectional-SPI-communication/m-p/175942#M6610</guid>
      <dc:creator>spearson</dc:creator>
      <dc:date>2012-11-21T02:01:27Z</dc:date>
    </item>
    <item>
      <title>Re: Bidirectional SPI communication</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Bidirectional-SPI-communication/m-p/175943#M6611</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;All,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Now, I am using L2.6.35_1.1.0-BSP.&lt;/P&gt;&lt;P&gt;I also have the same problem as you.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is this problem solved in mainline kernel?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;George&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 07 Jan 2014 14:03:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Bidirectional-SPI-communication/m-p/175943#M6611</guid>
      <dc:creator>george</dc:creator>
      <dc:date>2014-01-07T14:03:20Z</dc:date>
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