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    <title>topic Re: About Power sequence in i.MX6SL. in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/About-Power-sequence-in-i-MX6SL/m-p/429626#M65308</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; Internal sequencing basically does not depend on external voltage &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;supply sequence, assuming that corresponding inputs are provided :&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &lt;SPAN style="font-size: 12.0pt; font-family: 'Verdana','sans-serif';"&gt;VDD_HIGH_IN should be applied to get VDD_HIGH_CAP.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 28 Oct 2015 08:33:47 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2015-10-28T08:33:47Z</dc:date>
    <item>
      <title>About Power sequence in i.MX6SL.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-Power-sequence-in-i-MX6SL/m-p/429621#M65303</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear All,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hello. I have a question about Power sequence in i.MX6SL.&lt;/P&gt;&lt;P&gt;Refer to Table 7-3. Power sequence in Hardware Development Guide for i.MX 6SoloLite Applications Processor, Rev. 1.&lt;/P&gt;&lt;P&gt;There are two kind of power sequence at the Using all internal LDOs and Bypassed.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Q1]&lt;/P&gt;&lt;P&gt;At the time of Power sequence, does the internal LDOs become invalid?&lt;/P&gt;&lt;P&gt;(Why are there two kind of sequence?)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Q2]&lt;/P&gt;&lt;P&gt;Which correct description Data sheet or Hardware Design Guide?&lt;/P&gt;&lt;P&gt;(Description in Hardware Design Guide was hard requirement.)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Keita&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 27 Oct 2015 00:55:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-Power-sequence-in-i-MX6SL/m-p/429621#M65303</guid>
      <dc:creator>keitanagashima</dc:creator>
      <dc:date>2015-10-27T00:55:05Z</dc:date>
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    <item>
      <title>Re: About Power sequence in i.MX6SL.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-Power-sequence-in-i-MX6SL/m-p/429622#M65304</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; The Datasheet provides most general approach / requirements for power &lt;BR /&gt; up sequence ; the Development Guide shows recommended example of power &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;sequencing. Different power up sequence for LDO enable and bypass is recommended&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;mainly to avoid excessive current during power-up phase.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 27 Oct 2015 07:43:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-Power-sequence-in-i-MX6SL/m-p/429622#M65304</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-10-27T07:43:23Z</dc:date>
    </item>
    <item>
      <title>Re: About Power sequence in i.MX6SL.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-Power-sequence-in-i-MX6SL/m-p/429623#M65305</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hello. Thank you for your reply.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt;&amp;nbsp; The Datasheet provides most general approach / requirements for power &lt;/P&gt;&lt;P&gt;&amp;gt; up sequence ; the Development Guide shows recommended example of power&lt;/P&gt;&lt;P&gt;&amp;gt; sequencing. &lt;/P&gt;&lt;P&gt;OK. I got it.&lt;/P&gt;&lt;P&gt;For example, VDD_HIGH_IN and NVCC33_IO were same timing from Development Guide.&lt;/P&gt;&lt;P&gt;But, these can separate the power sequence from data sheet.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt; Different power up sequence for LDO enable and bypass is recommended&lt;/P&gt;&lt;P&gt;&amp;gt; mainly to avoid excessive current during power-up phase.&lt;/P&gt;&lt;P&gt;Sorry, I didn't understand it well.&lt;/P&gt;&lt;P&gt;How should one disable (bypass) the LDOs at the power-up phase.&lt;/P&gt;&lt;P&gt;My understanding was below.&lt;/P&gt;&lt;P&gt; Power-up phase is during POR_B asserted and the user can't select the bypass LDOs.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Keita&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 27 Oct 2015 08:20:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-Power-sequence-in-i-MX6SL/m-p/429623#M65305</guid>
      <dc:creator>keitanagashima</dc:creator>
      <dc:date>2015-10-27T08:20:32Z</dc:date>
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    <item>
      <title>Re: About Power sequence in i.MX6SL.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-Power-sequence-in-i-MX6SL/m-p/429624#M65306</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; Basically You are right : i.MX6 internal PMU enables LDO by default, so the &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;external input value must meet LDO enable mode requirement during power up.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;After booting, SW can change to LDO bypass mode. In this sense it would be &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;better to remove the power up recommendations for LDO bypass mode.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 27 Oct 2015 09:07:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-Power-sequence-in-i-MX6SL/m-p/429624#M65306</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-10-27T09:07:04Z</dc:date>
    </item>
    <item>
      <title>Re: About Power sequence in i.MX6SL.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-Power-sequence-in-i-MX6SL/m-p/429625#M65307</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hello. Thank you for your reply.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt;In this sense it would be better to remove the power up recommendations for LDO bypass mode.&lt;/P&gt;&lt;P&gt;I think so, too.&lt;/P&gt;&lt;P&gt;We would like to remove this description.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Let me clarify below thing.&lt;/P&gt;&lt;P&gt;Refer to Note.1 in Table 7-3. Power sequence of Data sheet.&lt;/P&gt;&lt;P&gt; "Internally controlled by processor."&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In case of the LDO enable (default), Power Up sequence looks controlled automatically by i.MX6.&lt;/P&gt;&lt;P&gt;If one power source supplies to i.MX6 with different sequence from "Table 7-3. Power sequence", does it become the sequence of "Table 7-3" by internal i.MX6?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Keita &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 27 Oct 2015 10:39:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-Power-sequence-in-i-MX6SL/m-p/429625#M65307</guid>
      <dc:creator>keitanagashima</dc:creator>
      <dc:date>2015-10-27T10:39:44Z</dc:date>
    </item>
    <item>
      <title>Re: About Power sequence in i.MX6SL.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-Power-sequence-in-i-MX6SL/m-p/429626#M65308</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; Internal sequencing basically does not depend on external voltage &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;supply sequence, assuming that corresponding inputs are provided :&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &lt;SPAN style="font-size: 12.0pt; font-family: 'Verdana','sans-serif';"&gt;VDD_HIGH_IN should be applied to get VDD_HIGH_CAP.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 28 Oct 2015 08:33:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-Power-sequence-in-i-MX6SL/m-p/429626#M65308</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-10-28T08:33:47Z</dc:date>
    </item>
    <item>
      <title>Re: About Power sequence in i.MX6SL.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-Power-sequence-in-i-MX6SL/m-p/429627#M65309</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for your reply.&lt;/P&gt;&lt;P&gt;&amp;gt;Internal sequencing basically does not depend on external voltage&lt;/P&gt;&lt;P&gt;&amp;gt;supply sequence&lt;/P&gt;&lt;P&gt;Is it possible to ignore the Table 7-3. Power sequence in HDG because the sequence is controlled by i.MX6 internally?&lt;/P&gt;&lt;P&gt;I think that the user must meet the power sequence in data sheet .&lt;/P&gt;&lt;P&gt;Is my understanding OK?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Keita&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 28 Oct 2015 08:54:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-Power-sequence-in-i-MX6SL/m-p/429627#M65309</guid>
      <dc:creator>keitanagashima</dc:creator>
      <dc:date>2015-10-28T08:54:03Z</dc:date>
    </item>
    <item>
      <title>Re: About Power sequence in i.MX6SL.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-Power-sequence-in-i-MX6SL/m-p/429628#M65310</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt; Yes, please follow Datasheet.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;~Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 30 Oct 2015 07:14:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-Power-sequence-in-i-MX6SL/m-p/429628#M65310</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-10-30T07:14:49Z</dc:date>
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