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    <title>topic DDR3 Trace Length in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/DDR3-Trace-Length/m-p/429030#M65194</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am designing a board with the i.MX6Q and (4) 2GBIT 800MHZ FBGA modules on board.&amp;nbsp; I have read the Hardware Development Guide from Freescale regarding keeping the trace lengths as equal in length as possible.&amp;nbsp; My question though is as follows:&amp;nbsp; The guide requests that I keep my clock traces to a max length of 2.25 inches and every other trace group smaller than that.&amp;nbsp; In my design, I can't keep my Address lines smaller than 4.5 inches in length for the group.&amp;nbsp; Where can I compromise the recommendations?&amp;nbsp; Do I make my clock lines at least 4.5 inches in length, or leave the clock lines as is and the address lines would just be longer than the clock?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks in advance,&lt;/P&gt;&lt;P&gt;Joseph&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 19 Nov 2015 20:41:43 GMT</pubDate>
    <dc:creator>Jochi119</dc:creator>
    <dc:date>2015-11-19T20:41:43Z</dc:date>
    <item>
      <title>DDR3 Trace Length</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DDR3-Trace-Length/m-p/429030#M65194</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am designing a board with the i.MX6Q and (4) 2GBIT 800MHZ FBGA modules on board.&amp;nbsp; I have read the Hardware Development Guide from Freescale regarding keeping the trace lengths as equal in length as possible.&amp;nbsp; My question though is as follows:&amp;nbsp; The guide requests that I keep my clock traces to a max length of 2.25 inches and every other trace group smaller than that.&amp;nbsp; In my design, I can't keep my Address lines smaller than 4.5 inches in length for the group.&amp;nbsp; Where can I compromise the recommendations?&amp;nbsp; Do I make my clock lines at least 4.5 inches in length, or leave the clock lines as is and the address lines would just be longer than the clock?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks in advance,&lt;/P&gt;&lt;P&gt;Joseph&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 19 Nov 2015 20:41:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DDR3-Trace-Length/m-p/429030#M65194</guid>
      <dc:creator>Jochi119</dc:creator>
      <dc:date>2015-11-19T20:41:43Z</dc:date>
    </item>
    <item>
      <title>Re: DDR3 Trace Length</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DDR3-Trace-Length/m-p/429031#M65195</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Joseph&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;in this case clock line should be increased up to 4.5 inches, so&lt;/P&gt;&lt;P&gt;when clock arrives all control/data were in proper place.&lt;/P&gt;&lt;P&gt;In general, if layout rules can not be followed, ibis modelling should be implemented&lt;/P&gt;&lt;P&gt;so all timings were calculated based on specific board conditions.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 20 Nov 2015 01:49:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DDR3-Trace-Length/m-p/429031#M65195</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-11-20T01:49:46Z</dc:date>
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