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    <title>i.MX ProcessorsのトピックRe: I2C loop back test in iMX6 CPU</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/I2C-loop-back-test-in-iMX6-CPU/m-p/428449#M65097</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Puneeth&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;in the current thread , it is mentioned as it is possible - yes,&amp;nbsp; hardware supports it.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In below thread. &lt;A _jive_internal="true" data-containerid="2004" data-containertype="14" data-content-finding="Community" data-objectid="444831" data-objecttype="1" href="https://community.nxp.com/thread/444831"&gt;i.mx6 i2c set to slave?&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;it is mentioned that linux does not support it:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;"..Linux Manual :&lt;/P&gt;&lt;P&gt;The I2C driver does not support the I2C slave mode of operation."&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 12 Mar 2020 05:40:32 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2020-03-12T05:40:32Z</dc:date>
    <item>
      <title>I2C loop back test in iMX6 CPU</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/I2C-loop-back-test-in-iMX6-CPU/m-p/428445#M65093</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;STRONG&gt;Hello FSL,&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is it possible to do the I2C1 &amp;amp; I2C2 loop back test in same iMX6 processor ? &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Example, &lt;/P&gt;&lt;P&gt;&lt;SPAN style="text-decoration: underline;"&gt;Time T1&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;I2C1 is act as master and I2C2 is act as slave at time T1. So that master and slave can be communicated (example send and receive data) in same processor. Thus we can make sure that I2C1 master &amp;amp; I2C2 slave functionalities are working properly.&amp;nbsp; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="text-decoration: underline;"&gt;Time T2&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Similar way,&lt;/P&gt;&lt;P&gt;I2C1 is act as slave and I2C2 is act as master at time T2. So that master and slave can be communicated (example send and receive data) in same processor. Thus we can make sure that I2C1 slave &amp;amp; I2C2 master functionalities are working properly.&amp;nbsp; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Also here I have atathced the wiring diagram of the I2C loop back test. Could you review and share the feedback ?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="I2C1 &amp;amp; I2C2 Loop Test.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/3857i8458643017031E8E/image-size/large?v=v2&amp;amp;px=999" role="button" title="I2C1 &amp;amp; I2C2 Loop Test.png" alt="I2C1 &amp;amp; I2C2 Loop Test.png" /&gt;&lt;/span&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Regards,&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Azlum&lt;/STRONG&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 04 Jun 2015 08:58:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/I2C-loop-back-test-in-iMX6-CPU/m-p/428445#M65093</guid>
      <dc:creator>mohammedazlum</dc:creator>
      <dc:date>2015-06-04T08:58:41Z</dc:date>
    </item>
    <item>
      <title>Re: I2C loop back test in iMX6 CPU</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/I2C-loop-back-test-in-iMX6-CPU/m-p/428446#M65094</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi mohammed&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes this is feasible test since i.MX6 I2C modules are&lt;/P&gt;&lt;P&gt;independent modules. One can work as master, while other&lt;/P&gt;&lt;P&gt;as slave and can communicate with each other.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 05 Jun 2015 00:21:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/I2C-loop-back-test-in-iMX6-CPU/m-p/428446#M65094</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-06-05T00:21:29Z</dc:date>
    </item>
    <item>
      <title>Re: I2C loop back test in iMX6 CPU</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/I2C-loop-back-test-in-iMX6-CPU/m-p/428447#M65095</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thank you for the support Igor !&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Azlum&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 05 Jun 2015 05:48:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/I2C-loop-back-test-in-iMX6-CPU/m-p/428447#M65095</guid>
      <dc:creator>mohammedazlum</dc:creator>
      <dc:date>2015-06-05T05:48:08Z</dc:date>
    </item>
    <item>
      <title>Re: I2C loop back test in iMX6 CPU</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/I2C-loop-back-test-in-iMX6-CPU/m-p/428448#M65096</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Need some clarification on this issue. You had mentioned that I2C slave mode functionality is not possible on IMX6 in the below thread.&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/444831"&gt;i.mx6 i2c set to slave?&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;But in the current thread , it is mentioned as it is possible to do the same.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I want to perform loopback test on i2c expansion connectors between i2c0 and i2c2(one as master and one as slave) on the IMX6 custom board. If it is possible, what are changes required to perform i2c loop-back test.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Any suggestions would be helpful.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Puneeth Kumar K&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Mar 2020 07:23:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/I2C-loop-back-test-in-iMX6-CPU/m-p/428448#M65096</guid>
      <dc:creator>puneethkumar_kk</dc:creator>
      <dc:date>2020-03-11T07:23:26Z</dc:date>
    </item>
    <item>
      <title>Re: I2C loop back test in iMX6 CPU</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/I2C-loop-back-test-in-iMX6-CPU/m-p/428449#M65097</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Puneeth&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;in the current thread , it is mentioned as it is possible - yes,&amp;nbsp; hardware supports it.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In below thread. &lt;A _jive_internal="true" data-containerid="2004" data-containertype="14" data-content-finding="Community" data-objectid="444831" data-objecttype="1" href="https://community.nxp.com/thread/444831"&gt;i.mx6 i2c set to slave?&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;it is mentioned that linux does not support it:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;"..Linux Manual :&lt;/P&gt;&lt;P&gt;The I2C driver does not support the I2C slave mode of operation."&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Mar 2020 05:40:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/I2C-loop-back-test-in-iMX6-CPU/m-p/428449#M65097</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2020-03-12T05:40:32Z</dc:date>
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