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<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
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    <title>topic Re: i.MX53 IPU Deinterlacer in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175500#M6503</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;BR /&gt;
&lt;BR /&gt;
&lt;CITE&gt;iWave Systems Technologies said:&lt;/CITE&gt;
&lt;BLOCKQUOTE cite="http://imxcommunity.org/forum/topics/i-mx53-ipu-deinterlacer?commentId=4103961%3AComment%3A39211&amp;amp;xg_source=msg_com_forum#4103961Comment39211"&gt;&lt;DIV&gt;&lt;DIV class="xg_user_generated"&gt;&lt;P&gt;Eric,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;We need de-interlace support in i.MX51 CSI1 interface &amp;amp; we are struggling to bring-up.&lt;/P&gt;
&lt;P&gt;Can you share the de-interlacing support on i.mx51CSI1 interface+ADV7180?&lt;/P&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/BLOCKQUOTE&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Hi~~&lt;/P&gt;
&lt;P&gt;Are you porting in Wince ?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;we 're just debugging now since HW ready in these day.As i know ADV7180 is use I2C command to control this chip.&lt;/P&gt;
&lt;P&gt;can you read chip-set staus?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;the otherwise,do you have&amp;nbsp;record software (API).&lt;/P&gt;
&lt;P&gt;Eric&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sat, 22 Oct 2011 08:49:55 GMT</pubDate>
    <dc:creator>DualDisplayiss1</dc:creator>
    <dc:date>2011-10-22T08:49:55Z</dc:date>
    <item>
      <title>i.MX53 IPU Deinterlacer</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175495#M6498</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;Has anyone come across a white paper or a Linux driver which implements the HW deinterlacer found in the i.MX53?&amp;nbsp; After getting an ADV7180 running on CSI1, I now have odd/even fields that need to be combined (preferably using the IPU).&amp;nbsp; For a quick demo using the unit_tests&amp;nbsp;it's easy just to crop and scale, but I'd really like to see the IPU do the heavy lifting.&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 05 Oct 2011 23:38:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175495#M6498</guid>
      <dc:creator>CraigPetku</dc:creator>
      <dc:date>2011-10-05T23:38:13Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX53 IPU Deinterlacer</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175496#M6499</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Do you mind use i.mx51CSI1 interface+ADV7180?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Eric&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 16 Oct 2011 04:29:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175496#M6499</guid>
      <dc:creator>DualDisplayiss1</dc:creator>
      <dc:date>2011-10-16T04:29:04Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX53 IPU Deinterlacer</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175497#M6500</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I haven't found good documentation on this yet, but while trying to get a ADV7180 up in Android I discovered the CSI-&amp;gt;MEM path appears to be deinterlacing video on the fly.&amp;nbsp; Unfortunately it's not aligning the two frames properly and&amp;nbsp;&amp;nbsp;I have VSYNC issues.&amp;nbsp; The partial de-interlacing results in no chroma&amp;nbsp;where the frames don't align.&amp;nbsp; Changing the ADV register settings per their DS results in better algnment (defaults have every other fame really deinterlaced poorly), but still not correct (and still not v-synced)&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Askng FSL for detailed information&amp;nbsp;on the CSI and IPU configuration but it's slow getting a reply.&amp;nbsp; The CCIR registers in the CSI block are not documented for bit order or why there are two blanking fields per frame.&amp;nbsp; This makes verifying that they are setup correctly almost impossible, but the reference code seems reasonable ofter compiling several variations of CCIR code bit orders and testing them to see which ones are potential fits.&amp;nbsp; The naming convention for fields in the CCIR registers does not appear to be be&amp;nbsp;imply correct ordering for the H,&amp;nbsp;F and&amp;nbsp;V bits. The only thing keeping me sane on all the compiles is having a fast quad core laptop.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Placing printk's everwhere I don't see where the CSI is linking to the VDIC and the SMFC doesn't appear to be throwing away frames and rescaling.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Also of interest is the PRP path (tested with the mxc_v4l2_overlay unit test) works fine (good hsync) but the CSI_ENC route fails to sync. I've tried going to progressive mode hoping to just see interleaved data, but that fails to VSYNC as well (picture rolls). Attempts to change the mx5x/libcamera routines to use the PRP path (changing the input from 1 to 0) fail with no video captured.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I would even consider&amp;nbsp;trying gated mode to get rid of the sync issue, but the RM and UG have no verified timing diagrams to demonstrate signal polarities and porch requirements.&amp;nbsp; It's also unclear if the CSI would discard&amp;nbsp; the embedded codes based upon an external hsync.&amp;nbsp;I'm guessing this would require a logic analyzer to verify the h-v sync timing is properly aligned with the SAV and EAV codes unless FSL can state that it would treat this as YUV data (even though the values would be out of range).&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Has anyone sucessfully integrated an adv7180 with Android yet?&amp;nbsp;&amp;nbsp;&amp;nbsp; I'm starting to wonder if CSI1 on the i.MX53 has an issue with AV codes...&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 20 Oct 2011 02:31:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175497#M6500</guid>
      <dc:creator>CraigPetku</dc:creator>
      <dc:date>2011-10-20T02:31:03Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX53 IPU Deinterlacer</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175498#M6501</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Eric,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;We need de-interlace support in i.MX51 CSI1 interface &amp;amp; we are struggling to bring-up.&lt;/P&gt;
&lt;P&gt;Can you share the de-interlacing support on i.mx51CSI1 interface+ADV7180?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 21 Oct 2011 06:00:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175498#M6501</guid>
      <dc:creator>iWave</dc:creator>
      <dc:date>2011-10-21T06:00:11Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX53 IPU Deinterlacer</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175499#M6502</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;So hunting through the code today I found the csi_enc routines seem to do their de-interlacing using the idmac in ipu_common.c.&amp;nbsp; Still looking for my cause of video rolling which is starting to look like the idmac&amp;nbsp; My&amp;nbsp;updates are still too rough to post.&amp;nbsp; Hopefully I'll have this figured out before Thursday.&amp;nbsp; If so I'll send a note to Zafeer.&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 22 Oct 2011 01:55:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175499#M6502</guid>
      <dc:creator>CraigPetku</dc:creator>
      <dc:date>2011-10-22T01:55:30Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX53 IPU Deinterlacer</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175500#M6503</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;BR /&gt;
&lt;BR /&gt;
&lt;CITE&gt;iWave Systems Technologies said:&lt;/CITE&gt;
&lt;BLOCKQUOTE cite="http://imxcommunity.org/forum/topics/i-mx53-ipu-deinterlacer?commentId=4103961%3AComment%3A39211&amp;amp;xg_source=msg_com_forum#4103961Comment39211"&gt;&lt;DIV&gt;&lt;DIV class="xg_user_generated"&gt;&lt;P&gt;Eric,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;We need de-interlace support in i.MX51 CSI1 interface &amp;amp; we are struggling to bring-up.&lt;/P&gt;
&lt;P&gt;Can you share the de-interlacing support on i.mx51CSI1 interface+ADV7180?&lt;/P&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/BLOCKQUOTE&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Hi~~&lt;/P&gt;
&lt;P&gt;Are you porting in Wince ?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;we 're just debugging now since HW ready in these day.As i know ADV7180 is use I2C command to control this chip.&lt;/P&gt;
&lt;P&gt;can you read chip-set staus?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;the otherwise,do you have&amp;nbsp;record software (API).&lt;/P&gt;
&lt;P&gt;Eric&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 22 Oct 2011 08:49:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175500#M6503</guid>
      <dc:creator>DualDisplayiss1</dc:creator>
      <dc:date>2011-10-22T08:49:55Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX53 IPU Deinterlacer</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175501#M6504</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Ok, I got the&amp;nbsp;ADV7180 working with the Android camera app.&amp;nbsp; I'll have&amp;nbsp;several action items for my local rep (when I see him)&amp;nbsp;e.g., explain the synchronization strategy between the CSI port and the IDMAC in CSI-&amp;gt;MEM.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;It looks like in the CSI-&amp;gt;MEM path the CSI free runs and the IDMAC generates the camera call back every time it completes&amp;nbsp;capturing one frame of data without syncronizing SOF to the CSI port SAV code timing.&amp;nbsp; If so, there's potential for these to get out of sync.&lt;/P&gt;
&lt;P&gt;In the CSI-&amp;gt;IC path syncronization appears to be done&amp;nbsp;appropriately&amp;nbsp;resulting in a stable image always.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Of course this could just be the current state of Linux drivers and not a design limitation,.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Once you get the frames synced properly and adjust offsets to account for the porches, then the de-interlacer in the IDMAC will start to behave as well.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 22 Oct 2011 17:05:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175501#M6504</guid>
      <dc:creator>CraigPetku</dc:creator>
      <dc:date>2011-10-22T17:05:54Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX53 IPU Deinterlacer</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175502#M6505</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;Hi Craig,&lt;BR /&gt;
&lt;BR /&gt;
While we were doing some tests with TVP5147 and i.MX51's CSI, we realized that our CSI is not performing deinterlacing either and we are receiving the two fields of every frame as two separated image of about 240 lines each, and that they are being drawn together (I will upload a photo of this sceneario to explain myself better asap)... i found in this discussion that you had a similar situation with ADV7180... can you explain me how did you get the frames synced properly?&lt;BR /&gt;
&lt;BR /&gt;
Thanks,&lt;BR /&gt;
Lautaro&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 27 Oct 2011 06:33:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175502#M6505</guid>
      <dc:creator>LautaroCarmona1</dc:creator>
      <dc:date>2011-10-27T06:33:52Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX53 IPU Deinterlacer</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175503#M6506</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;To start with I am working with the 10.2 version of FSL android. However, looking at an older ltib release from 2010 it looks like ths has been out for awhile.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Look at .﻿﻿﻿﻿﻿﻿/drivers/mxc/ipu3/ipu_common.c. You should find something like...&lt;/P&gt;
&lt;P&gt;﻿﻿if (_ipu_chan_is_interlaced(channel)) {&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; _ipu_ch_param_set_interlaced_scan(dma_chan);&lt;BR /&gt;
&amp;nbsp;&amp;nbsp;&amp;nbsp; }&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;In my case this handles the CSI-MEM deinterlacing.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;So Where does the interlace parameter come from?...&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Look at mxc_v4l_open in ./drivers/media/video/mxc/capture&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Older distro's have something like&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;csi_param.pixclk_pol = ifparm.u.bt656.latch_clk_inv;&lt;BR /&gt; &lt;BR /&gt;
&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; /* Once we handle multiple inputs this will need to change. */&lt;BR /&gt;
&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; csi_param.csi = 0;&lt;BR /&gt;
&lt;BR /&gt;
&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; if (ifparm.u.bt656.mode&lt;BR /&gt;
&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; == V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT)&lt;BR /&gt;
&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; csi_param.data_width = IPU_CSI_DATA_WIDTH_8;&lt;BR /&gt;
&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; else if (ifparm.u.bt656.mode&lt;BR /&gt;
&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; == V4L2_IF_TYPE_BT656_MODE_NOBT_10BIT)&lt;BR /&gt;
&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; csi_param.data_width = IPU_CSI_DATA_WIDTH_10;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Newer ones include the magic parameter based upon a clock setting returned by the sensor driver.&amp;nbsp; Sorry I can't post the actual code tonight, so I'll try from work tomorrow.&amp;nbsp; Worst case, pull down the latest version of the linux OS and look in the mxc_capture around where I posted, then update your sensor driver to return a 0 (I think) in the parameter that results in interlaced video being identified.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 28 Oct 2011 00:04:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175503#M6506</guid>
      <dc:creator>CraigPetku</dc:creator>
      <dc:date>2011-10-28T00:04:42Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX53 IPU Deinterlacer</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175504#M6507</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I use imx51, android 10.3 with ADV7180.&lt;/P&gt;
&lt;P&gt;the unit test program : mxc_v4l2_tvin runs well , it output de-interlaced frame on screen.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;the de-interlace seems be done on the output path, not the capturing path.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 04 Nov 2011 03:12:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175504#M6507</guid>
      <dc:creator>charleschang</dc:creator>
      <dc:date>2011-11-04T03:12:42Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX53 IPU Deinterlacer</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175505#M6508</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear Craig,&lt;/P&gt;
&lt;P&gt;Hi! Thanks for your advice! I could not test it until today!&lt;/P&gt;
&lt;P&gt;As you suggested us, we&amp;nbsp;looked&amp;nbsp;at &lt;STRONG&gt;&lt;EM&gt;drivers/media/video/mxc/capture/mxc_v4l2_capture.c&lt;/EM&gt;&lt;/STRONG&gt;&amp;nbsp;and we found this piece of code:&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;/* This may not work on other platforms. Check when adding a new one.*/&lt;/P&gt;
&lt;P&gt;pr_debug(" clock_curr=mclk=%d\n", ifparm.u.bt656.clock_curr);&lt;BR /&gt; &lt;STRONG&gt;if (ifparm.u.bt656.clock_curr == 0) {&lt;/STRONG&gt;&lt;BR /&gt; &lt;STRONG&gt;csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED;&lt;/STRONG&gt;&lt;BR /&gt; &lt;STRONG&gt;}&lt;/STRONG&gt; else {&lt;BR /&gt; csi_param.clk_mode = IPU_CSI_CLK_MODE_GATED_CLK;&lt;BR /&gt; }&lt;BR /&gt; csi_param.pixclk_pol = ifparm.u.bt656.latch_clk_inv;&lt;/P&gt;
&lt;P&gt;if (ifparm.u.bt656.mode == V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT) {&lt;BR /&gt; csi_param.data_width = IPU_CSI_DATA_WIDTH_8;&lt;BR /&gt; } else if (ifparm.u.bt656.mode== V4L2_IF_TYPE_BT656_MODE_NOBT_10BIT) {&lt;BR /&gt; csi_param.data_width = IPU_CSI_DATA_WIDTH_10;&lt;BR /&gt; } else {&lt;BR /&gt; csi_param.data_width = IPU_CSI_DATA_WIDTH_8;&lt;BR /&gt; }&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;So, we assumed that the clock setting you were talking about was&amp;nbsp;&lt;STRONG&gt;ifparm.u.bt656.clock_curr&lt;/STRONG&gt; .&lt;/P&gt;
&lt;P&gt;Then, we modified our driver in order to set this value to return a 0, like this:&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)&lt;/P&gt;
&lt;P&gt;{&lt;BR /&gt; #ifdef DEBUG&lt;BR /&gt; printk("In tvp5147:ioctl_g_ifparm\n");&lt;BR /&gt; #endif&lt;/P&gt;
&lt;P&gt;if (s == NULL) {&lt;BR /&gt; printk("&amp;lt;3&amp;gt;"" ERROR!! no slave device set!\n");&lt;BR /&gt; return -1;&lt;BR /&gt; }&lt;/P&gt;
&lt;P&gt;/* Initialize structure to 0s then set any non-0 values. */&lt;BR /&gt; memset(p, 0, sizeof(*p));&lt;BR /&gt; p-&amp;gt;if_type = V4L2_IF_TYPE_BT656; /* This is the only possibility.*/&lt;BR /&gt; p-&amp;gt;u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_BT_10BIT;&lt;BR /&gt; //p-&amp;gt;u.bt656.nobt_hs_inv = 1;&lt;BR /&gt; p-&amp;gt;u.bt656.bt_sync_correct = 1;&lt;/P&gt;
&lt;P&gt;/* tvp5147 has a dedicated clock so no clock settings needed. */&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;p-&amp;gt;u.bt656.clock_curr = 0;&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;return 0;&lt;BR /&gt; }&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;And then we also add some printk's in mxc_v4l2_capture.c :&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;if (ifparm.u.bt656.clock_curr == 0) {&lt;/P&gt;
&lt;P&gt;csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED;&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;printk("INTERLACED!!\n");&lt;/STRONG&gt;&lt;BR /&gt; }&amp;nbsp;else {&lt;BR /&gt; csi_param.clk_mode = IPU_CSI_CLK_MODE_GATED_CLK;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="white-space: pre;"&gt;&lt;STRONG&gt;printk("NOT INTERLACED!!\n");&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;BR /&gt; }&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Finally, we run&amp;nbsp;the &lt;STRONG&gt;mxc_v4l2_overlay.out&lt;/STRONG&gt;&amp;nbsp;and &lt;STRONG&gt;mxc_v4l2_capture.out&lt;/STRONG&gt; unit tests, but in both cases we saw the same results: two separated image of about 288 lines each vertically aligned (instead of one unique image of 576 lines), and in the serial console we could see the printk output &lt;STRONG&gt;"INTERLACED!!"&lt;/STRONG&gt;.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Any ideas?&lt;/P&gt;
&lt;P&gt;Thanks in advance,&lt;/P&gt;
&lt;P&gt;Lautaro&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;P.S.: We still have to try to capture using the csi-&amp;gt;mem path&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;
&lt;CITE&gt;Craig Petku said:&lt;/CITE&gt;&lt;/P&gt;
&lt;BLOCKQUOTE cite="http://imxcommunity.org/forum/topics/i-mx53-ipu-deinterlacer?xg_source=activity#4103961Comment40501"&gt;&lt;DIV&gt;&lt;DIV class="xg_user_generated"&gt;&lt;P&gt;To start with I am working with the 10.2 version of FSL android. However, looking at an older ltib release from 2010 it looks like ths has been out for awhile.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Look at .﻿﻿﻿﻿﻿﻿/drivers/mxc/ipu3/ipu_common.c. You should find something like...&lt;/P&gt;
&lt;P&gt;﻿﻿if (_ipu_chan_is_interlaced(channel)) {&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; _ipu_ch_param_set_interlaced_scan(dma_chan);&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp; }&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;In my case this handles the CSI-MEM deinterlacing.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;So Where does the interlace parameter come from?...&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Look at mxc_v4l_open in ./drivers/media/video/mxc/capture&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Older distro's have something like&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;csi_param.pixclk_pol = ifparm.u.bt656.latch_clk_inv;&lt;BR /&gt; &lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; /* Once we handle multiple inputs this will need to change. */&lt;BR /&gt;
&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; csi_param.csi = 0;&lt;BR /&gt;
&lt;BR /&gt;
&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; if (ifparm.u.bt656.mode&lt;BR /&gt;
&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; == V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT)&lt;BR /&gt;
&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; csi_param.data_width = IPU_CSI_DATA_WIDTH_8;&lt;BR /&gt;
&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; else if (ifparm.u.bt656.mode&lt;BR /&gt;
&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; == V4L2_IF_TYPE_BT656_MODE_NOBT_10BIT)&lt;BR /&gt;
&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; csi_param.data_width = IPU_CSI_DATA_WIDTH_10;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Newer ones include the magic parameter based upon a clock setting returned by the sensor driver.&amp;nbsp; Sorry I can't post the actual code tonight, so I'll try from work tomorrow.&amp;nbsp; Worst case, pull down the latest version of the linux OS and look in the mxc_capture around where I posted, then update your sensor driver to return a 0 (I think) in the parameter that results in interlaced video being identified.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/BLOCKQUOTE&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 09 Nov 2011 02:41:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175505#M6508</guid>
      <dc:creator>LautaroCarmona1</dc:creator>
      <dc:date>2011-11-09T02:41:47Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX53 IPU Deinterlacer</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175506#M6509</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I use ADV7180 + imx51. &amp;nbsp;android 10.3.1&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;the unit test program mxc_v4l2_tvin runs well, it output de-interlaced frame on overlay. and no need to memcpy each frame.&lt;/P&gt;
&lt;P&gt;-- &amp;nbsp;the mxv_v4l2_tvin code is different fromt imx53. though they have the same filename.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;just a little bug , the default video standard is PAL, it sync fail when we input the NTSC video.&lt;/P&gt;
&lt;P&gt;and&amp;nbsp;&lt;/P&gt;
&lt;P&gt;sometime it hangs when video source is disappeared for a short period.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;
&lt;CITE&gt;iWavesystems said:&lt;/CITE&gt;&lt;/P&gt;
&lt;BLOCKQUOTE cite="http://imxcommunity.org/forum/topics/i-mx53-ipu-deinterlacer?commentId=4103961%3AComment%3A43137&amp;amp;xg_source=msg_com_forum#4103961Comment39211"&gt;&lt;DIV&gt;&lt;DIV class="xg_user_generated"&gt;&lt;P&gt;Eric,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;We need de-interlace support in i.MX51 CSI1 interface &amp;amp; we are struggling to bring-up.&lt;/P&gt;
&lt;P&gt;Can you share the de-interlacing support on i.mx51CSI1 interface+ADV7180?&lt;/P&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/BLOCKQUOTE&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 09 Nov 2011 05:50:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175506#M6509</guid>
      <dc:creator>charleschang</dc:creator>
      <dc:date>2011-11-09T05:50:54Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX53 IPU Deinterlacer</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175507#M6510</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Here is a picture of what we are capturing with&amp;nbsp;TVP5147 and i.MX51's CSI.&lt;/P&gt;
&lt;P&gt;It seems that the CSI is not performing deinterlacing and here it can be seen that we are receiving the two fields of every frame as two separated image of 288 lines each, and that they are being drawn together.&lt;/P&gt;
&lt;P&gt;To capture this raw video I executed this command:&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;/unit_tests/mxc_v4l2_capture.out -iw 720 -ih 576 -ow 720 -oh 576 -f UYVY -fr 15 test.yuv&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Then we played it with this other command :&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;mplayer -rawvideo w=720:h=576:fps=15mat=uyvy -demuxer rawvideo test.yuv&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;P.S.: we also tried with both possible values (&lt;STRONG&gt;0&lt;/STRONG&gt;&amp;nbsp;and &lt;STRONG&gt;1&lt;/STRONG&gt;)&amp;nbsp;to the "&lt;STRONG&gt;-i&lt;/STRONG&gt;" argument in order to try &lt;STRONG&gt;csi-&amp;gt;prp-&amp;gt;mem&lt;/STRONG&gt; and &lt;STRONG&gt;csi-&amp;gt;mem&lt;/STRONG&gt;&amp;nbsp;path with the same results! :(&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 13 Nov 2011 03:39:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175507#M6510</guid>
      <dc:creator>LautaroCarmona1</dc:creator>
      <dc:date>2011-11-13T03:39:21Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX53 IPU Deinterlacer</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175508#M6511</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I use TVP5151 + imx53&lt;/P&gt;
&lt;P&gt;&amp;nbsp;I use mxv_v4l2_tvin test app and in the output the image seen in the monitor "&lt;STRONG&gt;rolls&lt;/STRONG&gt;".&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I tried adding&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;p-&amp;gt;u.bt656.clock_curr = 0;&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;nothing works :-(&lt;STRONG&gt;&lt;BR /&gt;&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Any fix/workaround for this problem&amp;nbsp; ?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 24 Nov 2011 13:01:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175508#M6511</guid>
      <dc:creator>Ananth</dc:creator>
      <dc:date>2011-11-24T13:01:32Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX53 IPU Deinterlacer</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175509#M6512</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I was able to fix this problem by programming drivers/media/video/mxc/capture/mxc_v4l2_capture.c .active_top =13 to .active_top = 3. And i was able to view the video in a good form using&lt;/P&gt;
&lt;P&gt;mxc_v4l2_tvin.out -ow 720 -oh 480 -ol 20 -f UYVY&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;i was able to see a video &lt;A rel="nofollow" href="https://community.nxp.com/../topic/listForContributor?user=0b09rbetkwbmh" class="fn url"&gt;interlaced form of video as told by Lautaro Carmona&lt;/A&gt; by using mxc_v4l2_capture.out file.&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;Queries&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;1. I am looking for any method/patches in IMX53 to avoid frame rolling issue (other than mentioned fix).&lt;/P&gt;
&lt;P&gt;2. From my De-coder(tvp5147) i was able to get 720x480 but in my start of line and end of line i have some blank data getting appended.&lt;/P&gt;
&lt;P&gt;So i wish to crop it from 720 to 700 by programming 20 pixel skip from left. so i tried "-l" option in &amp;nbsp;mxc_v4l2_capture.out&lt;/P&gt;
&lt;P&gt;but it is not working ... Any suggestion for this problem ?&lt;/P&gt;
&lt;P&gt;3. i wish to take even lines frame and odd lines frame out of image. So i used -t as 240 and output dimension as 720x240 in mxc_v4l2_capture.out. My method it is not working ... Any suggestion for this problem ?&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 06 Jan 2012 11:40:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175509#M6512</guid>
      <dc:creator>Ananth</dc:creator>
      <dc:date>2012-01-06T11:40:24Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX53 IPU Deinterlacer</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175510#M6513</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;I was unable to get the VDI module working but as for the display issue we managed to fix that.&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;We had the issue where Field A and B were displayed one above the other.&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;We now see interlaced video whereby the two fields are put into memory by interleaving their repsective lines. Of course you will see "combing artefacts" but that is becuase the video needs to be de-interlaced; however, it has been sufficient for us to use it this way.&lt;BR /&gt;&lt;BR /&gt;The relevant entry is in the file ipu_common.c as mentioned earlier. If you ensure your IPU logical channel is calling the set_interlaced function, the memory writes will put the frames together as interleaved data not separate fields.&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 21 Feb 2012 16:03:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175510#M6513</guid>
      <dc:creator>WillSheppard</dc:creator>
      <dc:date>2012-02-21T16:03:07Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX53 IPU Deinterlacer</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175511#M6514</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;BR /&gt; Hi charles&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;I use imx51, android 10.2 with ADV7180. but &amp;nbsp;i found the screen rolling endless.&lt;/P&gt;
&lt;P&gt;how did you porting the adv7180 driver to android 10.2&lt;/P&gt;
&lt;P&gt;Is it need to modify the camera HAL?&lt;/P&gt;
&lt;P&gt;after I porting the adv7180 driver which is run normally on android 9.4 to android 10.2,&lt;/P&gt;
&lt;P&gt;i got a rolling screen.&lt;/P&gt;
&lt;P&gt;Could you give me some advice?&lt;/P&gt;
&lt;P&gt;thanks&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;&lt;CITE&gt;charles chang said:&lt;/CITE&gt;&lt;/P&gt;
&lt;BLOCKQUOTE cite="http://imxcommunity.org/forum/topics/i-mx53-ipu-deinterlacer#4103961Comment42311"&gt;&lt;DIV&gt;&lt;DIV class="xg_user_generated"&gt;&lt;P&gt;I use imx51, android 10.3 with ADV7180.&lt;/P&gt;
&lt;P&gt;the unit test program : mxc_v4l2_tvin runs well , it output de-interlaced frame on screen.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;the de-interlace seems be done on the output path, not the capturing path.&lt;/P&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/BLOCKQUOTE&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 08 Mar 2012 14:47:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175511#M6514</guid>
      <dc:creator>JackyHuang</dc:creator>
      <dc:date>2012-03-08T14:47:47Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX53 IPU Deinterlacer</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175512#M6515</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;It's been several months since I got into the guts of the camera HAL and ADV7180, but here's some general comments.&lt;/P&gt;
&lt;P&gt;The Gingerbread Camera HAL really wants a 4:3 aspect ratio.&amp;nbsp; The only format that I found would work was to have the 7180 report 720x480 back to V4L2 and ignore the fact that the frame is actually 525 lines.&amp;nbsp; This results in rolling video since the DMA buffer is configured for only 480 lines and the image is 525.&amp;nbsp; It also has terrible frame combining in the IPU routines.&amp;nbsp; One solution is to program the registers in the 7180 to only output 480 lines.&amp;nbsp; This can be done by carefully adjusting where the AV codes occur in the stream.&amp;nbsp; Once the blanked HS&amp;nbsp;lines are&amp;nbsp;discarded (on both fields) the IPU will do field combining which may result in combing artifacts but is usable in development.&amp;nbsp; The down side to this appears that iPOD video has slightly different timing and the first few lines get clipped.&amp;nbsp; A more robust approach would be to use the v4l2_capture routines to pull in 525 lines and de-interlace the video before passing the 480 lines of interest up to the android camera routines.&amp;nbsp; I have not had time to implement this yet.&amp;nbsp; I also reversed the field1 / field0 codes in the IPU routines since they seemed to be backwards, but this is not confirmed and the RM is of little use in interpreting the bitfields for the AV codes.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 09 Mar 2012 00:11:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175512#M6515</guid>
      <dc:creator>CraigPetku</dc:creator>
      <dc:date>2012-03-09T00:11:50Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX53 IPU Deinterlacer</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175513#M6516</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Actually, I stop the screen rolling through &amp;nbsp;modify the adv7180 reg value, &amp;nbsp;the reg is about the NTSC V bit and F bit ,&amp;nbsp;&lt;/P&gt;
&lt;P&gt;the reg addr is 0xe5, 0xe6, 0xe7.&lt;/P&gt;
&lt;P&gt;however, &amp;nbsp;I got some&amp;nbsp;&amp;nbsp;sync issue that make the screen appear some&amp;nbsp;antialiasing.&lt;/P&gt;
&lt;P&gt;Are you resolve the issue&amp;nbsp;through &amp;nbsp;modify the adv7180 reg value?&lt;/P&gt;
&lt;P&gt;and, Could you explain how to&amp;nbsp;passing the 480 lines of interest data to&amp;nbsp;android camera routines?&lt;/P&gt;
&lt;P&gt;actually, I can't get the point about the&amp;nbsp;robust solution!&lt;/P&gt;
&lt;P&gt;Hope you can tell me the detail of you solution.&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;Thanks advance!&lt;BR /&gt; &lt;CITE&gt;Craig Petku said:&lt;/CITE&gt;&lt;/P&gt;
&lt;BLOCKQUOTE cite="http://imxcommunity.org/forum/topics/i-mx53-ipu-deinterlacer?xg_source=activity&amp;amp;id=4103961%3ATopic%3A36524&amp;amp;page=2#4103961Comment62770"&gt;&lt;DIV&gt;&lt;DIV class="xg_user_generated"&gt;&lt;P&gt;It's been several months since I got into the guts of the camera HAL and ADV7180, but here's some general comments.&lt;/P&gt;
&lt;P&gt;The Gingerbread Camera HAL really wants a 4:3 aspect ratio.&amp;nbsp; The only format that I found would work was to have the 7180 report 720x480 back to V4L2 and ignore the fact that the frame is actually 525 lines.&amp;nbsp; This results in rolling video since the DMA buffer is configured for only 480 lines and the image is 525.&amp;nbsp; It also has terrible frame combining in the IPU routines.&amp;nbsp; One solution is to program the registers in the 7180 to only output 480 lines.&amp;nbsp; This can be done by carefully adjusting where the AV codes occur in the stream.&amp;nbsp; Once the blanked HS&amp;nbsp;lines are&amp;nbsp;discarded (on both fields) the IPU will do field combining which may result in combing artifacts but is usable in development.&amp;nbsp; The down side to this appears that iPOD video has slightly different timing and the first few lines get clipped.&amp;nbsp; A more robust approach would be to use the v4l2_capture routines to pull in 525 lines and de-interlace the video before passing the 480 lines of interest up to the android camera routines.&amp;nbsp; I have not had time to implement this yet.&amp;nbsp; I also reversed the field1 / field0 codes in the IPU routines since they seemed to be backwards, but this is not confirmed and the RM is of little use in interpreting the bitfields for the AV codes.&lt;/P&gt;
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      <pubDate>Fri, 09 Mar 2012 11:04:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175513#M6516</guid>
      <dc:creator>JackyHuang</dc:creator>
      <dc:date>2012-03-09T11:04:25Z</dc:date>
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      <title>Re: i.MX53 IPU Deinterlacer</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175514#M6517</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;/P&gt;
&lt;P&gt;I am using TV-in application.it is working fine for PAL but for NTSC,screen rolls :(&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;I am working on tvp5150 decoder driver and what registers have to set/modify to stop the the screen rolling for NTSC.&lt;/P&gt;
&lt;P&gt;thanks,&lt;/P&gt;
&lt;BLOCKQUOTE cite="http://imxcommunity.org/forum/topics/i-mx53-ipu-deinterlacer?commentId=4103961%3AComment%3A46551#4103961Comment62770"&gt;&lt;DIV&gt;&lt;DIV class="xg_user_generated"&gt;&lt;/DIV&gt;
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      <pubDate>Wed, 18 Apr 2012 05:09:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX53-IPU-Deinterlacer/m-p/175514#M6517</guid>
      <dc:creator>mithunk</dc:creator>
      <dc:date>2012-04-18T05:09:57Z</dc:date>
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