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    <title>i.MX ProcessorsのトピックRe: EIM interface</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/EIM-interface/m-p/426416#M64622</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;this is continuation from my last reply&lt;/P&gt;&lt;P&gt;even default to lower half i am making them lower half through arm ds5 also&lt;/P&gt;&lt;P&gt;one thing i need clarification, i am using Cypress SRAM, in this case is it Sufficient to Change CONFIG_SYS_TEXT_BASE to 0x0c000000 (where my SRAM located on CS1) and ( instead of&amp;nbsp; 0x17800000 ddr address). i am interfacing SRAM in 32bit mode, any how NORFLASH boots from LowerHalf and PADS are done accordingly and for higher half i want to initialize IOMUX in u-boot, where before u-boot relocates to RAM. can you tell me where exaclty i need to add my assembly code in u-boot before relocation.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;thanks and regards&lt;/P&gt;&lt;P&gt;saida&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 10 Aug 2015 16:48:14 GMT</pubDate>
    <dc:creator>saida</dc:creator>
    <dc:date>2015-08-10T16:48:14Z</dc:date>
    <item>
      <title>EIM interface</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/EIM-interface/m-p/426413#M64619</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;hi&lt;/P&gt;&lt;P&gt;I.mx6 community&lt;/P&gt;&lt;P&gt;can any one help me in this regard&lt;/P&gt;&lt;P&gt;i have connected sram on eim bus and eim configured as half for NOR flash(64mb) and half for SRAM(32mb) and FPGA(32mb) for dualite&lt;/P&gt;&lt;P&gt;Register settings what i have done is&lt;/P&gt;&lt;P&gt;GPR1=0x4840001b&lt;/P&gt;&lt;P&gt;cs1 registers:(0x021b8018)&lt;/P&gt;&lt;P&gt;GCR1=0X00610081&lt;/P&gt;&lt;P&gt;GCR2=0X00001002&lt;/P&gt;&lt;P&gt;RCR1=0X1C022000&lt;/P&gt;&lt;P&gt;RCR2=0X0&lt;/P&gt;&lt;P&gt;WCR1=0X1C092480&lt;/P&gt;&lt;P&gt;WCR2=0X0&lt;/P&gt;&lt;P&gt;IOMUX (its default to lower half data bus)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;so when i try to write data to sram through ds5 debugger 1 and 3 nibble is not changing only 0 and 2 modifying accordingly&lt;/P&gt;&lt;P&gt;what could be the problem is there any register to set&lt;/P&gt;&lt;P&gt;and NOR FLASH is also connected on lower half databus&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;thanks and regards&lt;/P&gt;&lt;P&gt;saida&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 10 Aug 2015 08:51:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/EIM-interface/m-p/426413#M64619</guid>
      <dc:creator>saida</dc:creator>
      <dc:date>2015-08-10T08:51:28Z</dc:date>
    </item>
    <item>
      <title>Re: EIM interface</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/EIM-interface/m-p/426414#M64620</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi saida&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;can you confirm that iomux CSI0_x signals are set to ALT1:&lt;/P&gt;&lt;P&gt;for example EIM_DATA00 --&amp;gt; CSI0_DATA_EN (ALT1),&lt;/P&gt;&lt;P&gt;EIM_DATA01 --&amp;gt; CSI0_VSYNC (ALT1)&amp;nbsp;&amp;nbsp; .. ?&lt;/P&gt;&lt;P&gt;For GCR1=0X00610081 (DSZ=1), EIM data is allocated&lt;/P&gt;&lt;P&gt;on lower half bus: EIM_DATA0-15, these signals are muxed on&lt;/P&gt;&lt;P&gt;CSI0_DATx pads, which by default (out of reset) are configured as&lt;/P&gt;&lt;P&gt;GPIOs.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 10 Aug 2015 10:36:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/EIM-interface/m-p/426414#M64620</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-08-10T10:36:57Z</dc:date>
    </item>
    <item>
      <title>Re: EIM interface</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/EIM-interface/m-p/426415#M64621</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;thank you for your reply&lt;/P&gt;&lt;P&gt;i makeing CSIO_DATx pads are default to EIM_DATA lower half from EIM_BOOT that is NOR flash 16bit boot (A+LH) from page refmanual(DLRM)398,8.5.1 (10 option)&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 10 Aug 2015 16:29:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/EIM-interface/m-p/426415#M64621</guid>
      <dc:creator>saida</dc:creator>
      <dc:date>2015-08-10T16:29:22Z</dc:date>
    </item>
    <item>
      <title>Re: EIM interface</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/EIM-interface/m-p/426416#M64622</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;this is continuation from my last reply&lt;/P&gt;&lt;P&gt;even default to lower half i am making them lower half through arm ds5 also&lt;/P&gt;&lt;P&gt;one thing i need clarification, i am using Cypress SRAM, in this case is it Sufficient to Change CONFIG_SYS_TEXT_BASE to 0x0c000000 (where my SRAM located on CS1) and ( instead of&amp;nbsp; 0x17800000 ddr address). i am interfacing SRAM in 32bit mode, any how NORFLASH boots from LowerHalf and PADS are done accordingly and for higher half i want to initialize IOMUX in u-boot, where before u-boot relocates to RAM. can you tell me where exaclty i need to add my assembly code in u-boot before relocation.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;thanks and regards&lt;/P&gt;&lt;P&gt;saida&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 10 Aug 2015 16:48:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/EIM-interface/m-p/426416#M64622</guid>
      <dc:creator>saida</dc:creator>
      <dc:date>2015-08-10T16:48:14Z</dc:date>
    </item>
    <item>
      <title>Re: EIM interface</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/EIM-interface/m-p/426417#M64623</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;iomux configuration can be done in uboot flash_header.S&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;~igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Aug 2015 01:40:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/EIM-interface/m-p/426417#M64623</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-08-11T01:40:36Z</dc:date>
    </item>
    <item>
      <title>Re: EIM interface</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/EIM-interface/m-p/426418#M64624</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;have you seen my last post regarding SRAM to load u-boot&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;thanks and regards&lt;/P&gt;&lt;P&gt;saida&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Aug 2015 11:12:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/EIM-interface/m-p/426418#M64624</guid>
      <dc:creator>saida</dc:creator>
      <dc:date>2015-08-11T11:12:25Z</dc:date>
    </item>
    <item>
      <title>Re: EIM interface</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/EIM-interface/m-p/426419#M64625</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;if this problem is different from eim, then it should be&lt;/P&gt;&lt;P&gt;discussed in new thread.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Aug 2015 12:25:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/EIM-interface/m-p/426419#M64625</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-08-11T12:25:47Z</dc:date>
    </item>
    <item>
      <title>Re: EIM interface</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/EIM-interface/m-p/426420#M64626</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;hi&lt;/P&gt;&lt;P&gt;after spending time on SRAM i am out of trouble now&lt;/P&gt;&lt;P&gt;i solved the problem&lt;/P&gt;&lt;P&gt;thank you&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 19 Aug 2015 11:47:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/EIM-interface/m-p/426420#M64626</guid>
      <dc:creator>saida</dc:creator>
      <dc:date>2015-08-19T11:47:35Z</dc:date>
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