<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX Processors中的主题 Re: How does u-boot read dcd table?</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/How-does-u-boot-read-dcd-table/m-p/426236#M64576</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi eddie&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;iROM automatically seeks DCD data, based on boot settings,&lt;/P&gt;&lt;P&gt;boot flow similar to sect.7.6.2 Device Configuration Data (DCD) &lt;A href="http://cache.freescale.com/files/32bit/doc/ref_manual/iMX53RM.pdf?fasp=1&amp;amp;WT_TYPE=Reference%20Manuals&amp;amp;WT_VENDOR=FREESCALE&amp;amp;WT_FILE_FORMAT=pdf&amp;amp;WT_ASSET=Documentation&amp;amp;fileExt=.pdf"&gt;IMX53RM&lt;/A&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 25 Jun 2015 02:50:46 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2015-06-25T02:50:46Z</dc:date>
    <item>
      <title>How does u-boot read dcd table?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-does-u-boot-read-dcd-table/m-p/426234#M64574</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi there,&lt;/P&gt;&lt;P&gt;In U-boot of imx.51 I understand the start position of SD card booting is 0x400, and there's a command for cpu to jump to _start. However, all DCD entries reside between 0x400 and _start. So how does cpu come back and read these DCD entries to complete DDR controller configuration? Thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 24 Jun 2015 09:08:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-does-u-boot-read-dcd-table/m-p/426234#M64574</guid>
      <dc:creator>eddiehuang</dc:creator>
      <dc:date>2015-06-24T09:08:28Z</dc:date>
    </item>
    <item>
      <title>Re: How does u-boot read dcd table?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-does-u-boot-read-dcd-table/m-p/426235#M64575</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;nbsp; The boot ROM of the i.MX51 copies the whole block (2K / 4K) to internal memory&lt;/P&gt;&lt;P&gt;in order&amp;nbsp; to analyze it.&amp;nbsp;&amp;nbsp; Please refer to Figure 1 (Secure Boot Flow from Device) &lt;/P&gt;&lt;P&gt;of the app note AN4547 (&lt;SPAN style="font-size: 12.0pt; font-family: 'Verdana','sans-serif';"&gt;Secure Boot on i.MX25, i.MX35, and i.MX51 &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 12.0pt; font-family: 'Verdana','sans-serif';"&gt;using HABv3&lt;/SPAN&gt;)&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;A href="http://cache.freescale.com/files/32bit/doc/app_note/AN4547.pdf" title="http://cache.freescale.com/files/32bit/doc/app_note/AN4547.pdf"&gt;http://cache.freescale.com/files/32bit/doc/app_note/AN4547.pdf&lt;/A&gt; &lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 25 Jun 2015 02:25:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-does-u-boot-read-dcd-table/m-p/426235#M64575</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-06-25T02:25:56Z</dc:date>
    </item>
    <item>
      <title>Re: How does u-boot read dcd table?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-does-u-boot-read-dcd-table/m-p/426236#M64576</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi eddie&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;iROM automatically seeks DCD data, based on boot settings,&lt;/P&gt;&lt;P&gt;boot flow similar to sect.7.6.2 Device Configuration Data (DCD) &lt;A href="http://cache.freescale.com/files/32bit/doc/ref_manual/iMX53RM.pdf?fasp=1&amp;amp;WT_TYPE=Reference%20Manuals&amp;amp;WT_VENDOR=FREESCALE&amp;amp;WT_FILE_FORMAT=pdf&amp;amp;WT_ASSET=Documentation&amp;amp;fileExt=.pdf"&gt;IMX53RM&lt;/A&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 25 Jun 2015 02:50:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-does-u-boot-read-dcd-table/m-p/426236#M64576</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-06-25T02:50:46Z</dc:date>
    </item>
    <item>
      <title>Re: How does u-boot read dcd table?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-does-u-boot-read-dcd-table/m-p/426237#M64577</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Appreciate that. I did this study for a while and I was assuming the memory controller will be set in lowlevel_init.S. Does it mean memory controller configurations are done before _reset? It looks dcd are done in the very first beginning!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 25 Jun 2015 05:26:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-does-u-boot-read-dcd-table/m-p/426237#M64577</guid>
      <dc:creator>eddiehuang</dc:creator>
      <dc:date>2015-06-25T05:26:12Z</dc:date>
    </item>
  </channel>
</rss>

