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    <title>topic Re: ECSPI2 RXDATA = 0x00 in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/ECSPI2-RXDATA-0x00/m-p/424889#M64284</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I do not think that pad control can influence on that,&lt;/P&gt;&lt;P&gt;suggest to look at spi examples in obds&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 12 Aug 2015 01:59:41 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2015-08-12T01:59:41Z</dc:date>
    <item>
      <title>ECSPI2 RXDATA = 0x00</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/ECSPI2-RXDATA-0x00/m-p/424886#M64281</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I am using a MCIMX536AVV8C custom board borrowed from a previous project with a working product, and am attempting to write a new SPI driver for my c application.&amp;nbsp; Using a scope when I transmit SPI, I can see good data goes out on the MOSI and good data comes back on the MISO.&amp;nbsp; The observed signal swings from 0 to 3.3 volts correctly.&amp;nbsp; However, the RXDATA register is always zero.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have tried moving the wiring to CSPI port, same issue. RXDATA is always 0x00.&amp;nbsp; I also tried setting the MISO pin mux to GPIO as an input.&amp;nbsp; It functions as expected when I inject a signal, so at least I know my wiring is good.&amp;nbsp; But when configured as MISO, I inject 3.3 volts during the SPI transfer and still read 0x00 in the buffer.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Code is below.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;PRE __default_attr="c++" __jive_macro_name="code" class="_jivemacro_uid_14391253265267366 jive_macro_code jive_text_macro" data-renderedposition="197_8_1155_1280" jivemacro_uid="_14391253265267366"&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;void InitializeECSPI2 (void)&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;{&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; //MUX&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT8_bit.MUX_MODE = 3;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; //T1 ECSPI2 CLK&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT9_bit.MUX_MODE = 3;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; //R4 ECSPI2 MOSI&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT10_bit.MUX_MODE = 3;&amp;nbsp;&amp;nbsp;&amp;nbsp; //R5 ECSPI2 MISO&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; IOMUXC_SW_PAD_CTL_PAD_CSI0_DAT10 = 0x1C4;&amp;nbsp;&amp;nbsp;&amp;nbsp; //R5, Pull Down (input)&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; ECSPI2_CONREG_bit.CHANNEL_SELECT&amp;nbsp; = 0;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; //clock&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; ECSPI2_CONREG_bit.PRE_DIVIDER&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; ECSPI2_CONREG_bit.POST_DIVIDER&amp;nbsp;&amp;nbsp;&amp;nbsp; = 9; // (9) divide by 512&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; /* all channels set to master mode */&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; ECSPI2_CONREG_bit.CHANNEL_MODE&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0xF; //set all channels&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; /* Set LEN bits to transfer.&amp;nbsp; */&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; ECSPI2_CONREG_bit.BURST_LENGTH = 7;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; /* Disable SPI to reset&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; */&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; ECSPI2_CONREG_bit.EN = 1;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; /* clear the bit */&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; ECSPI2_CONFIGREG_bit.SCLK_PHA = 0;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; ECSPI2_CONFIGREG_bit.SCLK_POL = 0;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; /* set the bit */&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; ECSPI2_CONFIGREG_bit.SS_CTL = 1 ;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; /* Chip select polarity 0 = active low&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; */&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; ECSPI2_CONFIGREG_bit.SS_POL&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; /* Set DATA to say low between xfers&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; */&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; ECSPI2_CONFIGREG_bit.DATA_CTL&amp;nbsp;&amp;nbsp;&amp;nbsp; = 1;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; /* Set SCLK to say low between xfers&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; */&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; ECSPI2_CONFIGREG_bit.SCLK_CTL&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; /* Set LEN bits to tradevnsfer. */&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; ECSPI2_CONFIGREG_bit.HT_LENGTH&amp;nbsp;&amp;nbsp; = 0xF;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; ECSPI2_CONREG_bit.HT&amp;nbsp;&amp;nbsp; = 0;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; /* Enable transfer complete interrupt&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; */&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; ECSPI2_INTREG_bit.TCEN&amp;nbsp;&amp;nbsp; = 1;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; /* Enable RX FIFO overflow interrupt&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; */&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; ECSPI2_INTREG_bit.ROEN&amp;nbsp;&amp;nbsp; = 1;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; /* Enable TX FIFO empty interrupt&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; */&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; ECSPI2_INTREG_bit.TEEN&amp;nbsp;&amp;nbsp; = 1;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; /* Set XCH mode (waits for flag before sending) */&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; ECSPI2_CONREG_bit.SMC&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;}&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;uint32_t ECSPI2Transfer( uint8_t tx_byte, uint8_t rx_expected )&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;{ &lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; //note: CS is set outside of the tx function&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; uint32_t receiveData = 0; &lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; ECSPI2_CONREG_bit.BURST_LENGTH = 7;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; ECSPI2_CONREG_bit.CHANNEL_SELECT = 0;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; ECSPI2_CONREG_bit.EN&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 1;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* enable spi&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; */&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; ECSPI2_TXDATA&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = tx_byte;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Tx data&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; */&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; ECSPI2_CONREG_bit.XCH&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 1;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* set xch bit&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; */&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; /* poll on the TC bit (transfer complete) */&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; while (ECSPI2_STATREG_bit.TC == 0);&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; ECSPI2_STATREG_bit.TC = 1; /* Reset TC bit */&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; receiveData = ECSPI2_RXDATA;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;&amp;nbsp; return (receiveData); //receivedString&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-family: 'courier new', courier; font-size: 8pt;"&gt;}&lt;/SPAN&gt;&lt;/P&gt;&lt;/PRE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Mysterious side note. When I flash the binary from the previous working application, let run, then without power cycling I download my application to ram, I do get non-zero RXDATA in the buffer.&amp;nbsp; The numbers in RXDATA are wrong, but unlike my naked application, they are not 0x00.&amp;nbsp; It appears that the MISO input is reading any number of 0s, but only the first low to high transition.&amp;nbsp; Afterward, it only reads 1s and misses any high to low transitions.&amp;nbsp; Examples: 00,55,AA becomes 00,7F,FF, and 00,00,30 becomes 00,00,3F.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;This is also wrong, but at least it is not nothing.&amp;nbsp; Makes me suspect that a register setting outside of the registers listed in SPI init is affecting the MISO input.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 09 Aug 2015 13:17:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/ECSPI2-RXDATA-0x00/m-p/424886#M64281</guid>
      <dc:creator>dustinwestaby</dc:creator>
      <dc:date>2015-08-09T13:17:15Z</dc:date>
    </item>
    <item>
      <title>Re: ECSPI2 RXDATA = 0x00</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/ECSPI2-RXDATA-0x00/m-p/424887#M64282</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Dustin&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for usage CSI0_DAT10 as&amp;nbsp; ECSPI2 MISO one also needs&lt;/P&gt;&lt;P&gt;to set daisy chain with register IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT,&lt;/P&gt;&lt;P&gt;described in sect.43.3.492 IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT&lt;/P&gt;&lt;P&gt;(IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT) i.MX53 Reference Manual (rev.2.1&amp;nbsp; 6/2012)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="http://www.freescale.com/files/32bit/doc/ref_manual/iMX53RM.pdf" rel="nofollow"&gt;http://www.freescale.com/files/32bit/doc/ref_manual/iMX53RM.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for spi test codes one can look at i.MX53 OBDS on &lt;/P&gt;&lt;P&gt;Lab and Test Software (2)&lt;/P&gt;&lt;P&gt;&lt;A href="http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX53QSB&amp;amp;fpsp=1&amp;amp;tab=Design_Tools_Tab" title="http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX53QSB&amp;amp;fpsp=1&amp;amp;tab=Design_Tools_Tab"&gt;i.MX53 Quick Start Board|Freescale&lt;/A&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Aug 2015 00:58:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/ECSPI2-RXDATA-0x00/m-p/424887#M64282</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-08-11T00:58:05Z</dc:date>
    </item>
    <item>
      <title>Re: ECSPI2 RXDATA = 0x00</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/ECSPI2-RXDATA-0x00/m-p/424888#M64283</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Ah, so there &lt;EM&gt;was&lt;/EM&gt; another register I was missing.&amp;nbsp; Thanks.&amp;nbsp; That gets my application receiving SPI to the ECSPI2_RXDATA buffer all by itself.&amp;nbsp; However, the data received is still bad.&lt;/P&gt;&lt;BLOCKQUOTE&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif;"&gt;The numbers in RXDATA are wrong.&amp;nbsp; It appears that the MISO input is reading any number of 0s, but only the first low to high transition.&amp;nbsp; Afterward, it only reads 1s and misses any high to low transitions.&amp;nbsp; Examples: 00,55,AA becomes 00,7F,FF, and 00,00,30 becomes 00,00,3F.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;Would anything in pad control do that?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Aug 2015 16:02:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/ECSPI2-RXDATA-0x00/m-p/424888#M64283</guid>
      <dc:creator>dustinwestaby</dc:creator>
      <dc:date>2015-08-11T16:02:22Z</dc:date>
    </item>
    <item>
      <title>Re: ECSPI2 RXDATA = 0x00</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/ECSPI2-RXDATA-0x00/m-p/424889#M64284</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I do not think that pad control can influence on that,&lt;/P&gt;&lt;P&gt;suggest to look at spi examples in obds&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 12 Aug 2015 01:59:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/ECSPI2-RXDATA-0x00/m-p/424889#M64284</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-08-12T01:59:41Z</dc:date>
    </item>
    <item>
      <title>Re: ECSPI2 RXDATA = 0x00</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/ECSPI2-RXDATA-0x00/m-p/424890#M64285</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks for the reply.&amp;nbsp; I looked at the imx_ecspi.c file from the On-Board Diagnostic Suite.&amp;nbsp; Following the spi transfer example and keeping my working init function, I only see 0x00 in the receive buffer.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The difference in my code vs the example is that I am sending a single byte and reading the rx buffer prior to sending the next byte.&amp;nbsp; Not using the FIFO.&amp;nbsp; and it works, but returns sticky bit data instead of the expected values.&amp;nbsp; Makes me think hw failure.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am going to stop troubleshooting this for a week or two.&amp;nbsp; Get some new hardware in and try again.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Example that uses FIFO from imx_ecspi.c converted to use the registers from Freescale/iomcimx535.h:&lt;/P&gt;&lt;PRE __default_attr="c++" __jive_macro_name="code" class="jive_macro_code _jivemacro_uid_14393940763466320 jive_text_macro" data-renderedposition="218_8_1155_416" jivemacro_uid="_14393940763466320" modifiedtitle="true"&gt;&lt;P&gt;int imx_ecspi_xfer(unsigned char *tx_buf,&amp;nbsp; int burst_bytes)&lt;/P&gt;&lt;P&gt;{&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; unsigned int *p_buf;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; int len, ret_val = 0;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; ECSPI2_CONREG_bit.EN&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 1; /* enable spi */&amp;nbsp; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; // move data to the tx fifo&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; for (p_buf = (unsigned int *)tx_buf, len = burst_bytes; len &amp;gt; 0; p_buf++, len -= 4) {&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ECSPI2_TXDATA = *p_buf;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; }&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; ECSPI2_CONREG_bit.XCH = 1;// set xch bit&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; // poll on the TC bit (transfer complete)&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; while (ECSPI2_STATREG_bit.TC == 0);&amp;nbsp; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; // clear the TC bit&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; ECSPI2_STATREG_bit.TC = 1;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; // move data in the rx buf&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; for (p_buf = (unsigned int *)tx_buf, len = burst_bytes; len &amp;gt; 0; p_buf++, len -= 4) {&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; *p_buf = ECSPI2_RXDATA;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; }&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; return ret_val;&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;/PRE&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 12 Aug 2015 15:47:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/ECSPI2-RXDATA-0x00/m-p/424890#M64285</guid>
      <dc:creator>dustinwestaby</dc:creator>
      <dc:date>2015-08-12T15:47:37Z</dc:date>
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