topic Re: Which frequency is correct for i.MX6SDLACLK_EIM_SLOW_CLK_ROOT? in i.MX Processors

Which frequency is correct for i.MX6SDLACLK_EIM_SLOW_CLK_ROOT?

satoshishimoda — Mon, 20 Apr 2015 09:10:39 GMT

Hi community,

We have a question about i.MX6SDL CCM.

Please see Table 18-3 in IMX6SDLRM Rev.1.

It shows ACLK_EIM_SLOW_CLK_ROOT = 198MHz (default).

However, according to the initial register setting of CCM_CSCMR1, it seems to be a half of AXI clock frequency (blue line in Figure 18-2).

And according to the initial register setting of CCM_CBCDR, AXI frequency is half of a half of PLL2 396MHz.

So we can get ACLK_EIM_SLOW_CLK_ROOT = 99MHz (a quater of PLL2 396MHz).

Which is correct?

Best Regards,

Satoshi Shimoda

Re: Which frequency is correct for i.MX6SDLACLK_EIM_SLOW_CLK_ROOT?

Yuri — Mon, 20 Apr 2015 09:49:01 GMT

By default, EIM ACLK (aclk_eim_slow) is sourced from AXI clock root (396MHz) with divide-by-2, so it is 198 MHz.

Have a great day,
Yuri

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Re: Which frequency is correct for i.MX6SDLACLK_EIM_SLOW_CLK_ROOT?

satoshishimoda — Tue, 21 Apr 2015 01:03:02 GMT

Hi Yuri,

Thank you for your reply.

According to your reply, it seems that our understanding about AXI bus frequency was wrong.

Maybe, I will create a new thread about AXI bus frequency.

Thank you.

Best Regards,

Satoshi Shimoda

Re: Which frequency is correct for i.MX6SDLACLK_EIM_SLOW_CLK_ROOT?

Rob_iMX6 — Fri, 04 Sep 2015 18:53:44 GMT

Hi Yuri

According to the datasheet of iMX.6SDL, ACLK_EIM_SLOW_CLK_ROOT must not exceed 132MHz (i:MX 6Solo/DualLite Rev.5, page 52).

Does this mean that the default clock is out of spec?

Best regards,

-Urs

Re: Which frequency is correct for i.MX6SDLACLK_EIM_SLOW_CLK_ROOT?

Yuri — Mon, 07 Sep 2015 06:46:53 GMT

Hello,

Looks like - yes, the default value should not be used.

Regards,

Yuri.

Re: Which frequency is correct for i.MX6SDLACLK_EIM_SLOW_CLK_ROOT?

Yuri — Thu, 12 Jan 2017 08:46:33 GMT

Hello,

For the recent RM - please refer to https://community.nxp.com/thread/442559

Regards,

Yuri.