i.MX ProcessorsのトピックRe: SSI output clock is not geterated randomly

SSI output clock is not geterated randomly

saurabh206 — Sat, 18 Apr 2015 05:05:10 GMT

Hello Experts,

We have setup SSI as a master mode and Audio codec in slave mode.

We are using 3.10.17 kernel.

Randomly we have seen that system doesn't output any sound, After probing the SSI clock we found that there is no signal on SSI clock.

Any suggestions what could be the issue? How to fixed this?

Thanks

Saurabh

Re: SSI output clock is not geterated randomly

igorpadykov — Mon, 20 Apr 2015 04:44:32 GMT

Hi Saurabh

one can check if i.MX6QD CCM_CCGR5 is configured properly

to work in low power modes. Also one can check if this is

caused by hardware - check chip reference clocks and power

supplies.

Best regards

igor

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Re: SSI output clock is not geterated randomly

saurabh206 — Mon, 20 Apr 2015 06:03:35 GMT

Hi Igor,

Thanks for your suggestions.

I have verified this register for both working and none working case and its values remains same.

CCM_CCGR5 = 0x0FF000C3

Thanks

Saurabh

Re: SSI output clock is not geterated randomly

igorpadykov — Mon, 20 Apr 2015 06:57:43 GMT

Hi Saurabh

I would suggest to output source of SSI clock

on CLKO pin and check if it stops.

Best regards

igor

Re: SSI output clock is not geterated randomly

saurabh206 — Mon, 20 Apr 2015 08:08:21 GMT

igor,

I have route to CLK02, and I cannot able to see the SSI clock.

What is possible root cause?

Thanks

Saurabh

Re: SSI output clock is not geterated randomly

igorpadykov — Mon, 20 Apr 2015 09:49:00 GMT

Hi Saurabh

what PLL is used as source ?

You can output PLL on CLK02

and check.

~igor

Re: SSI output clock is not geterated randomly

saurabh206 — Mon, 20 Apr 2015 10:06:52 GMT

Hi Igor,

I have used PLL4.

I will try PPL4 output to CLK02.

Thanks

Saurabh

Re: SSI output clock is not geterated randomly

saurabh206 — Mon, 20 Apr 2015 12:31:16 GMT

Hi Igor,

SSI3 is derived from PPL4 , and SSI3 clock is available.

So we can say the reference PLL is active.

Thanks

Saurabh

Re: SSI output clock is not geterated randomly

igorpadykov — Mon, 20 Apr 2015 16:16:32 GMT

Hi Saurabh

so if PLL4 is active all time,

where signal is lost on its path to SSI output clock ?

You can debug it further, probably outputting

to CLK02 appropriate signals.

~igor

Re: SSI output clock is not geterated randomly

saurabh206 — Tue, 21 Apr 2015 06:00:30 GMT

Hi Igor

How to debug further?

Only SSI2 is dead, remaining clocks are on.

Re: SSI output clock is not geterated randomly

igorpadykov — Tue, 21 Apr 2015 14:37:51 GMT

Hi Saurabh

if this is just one board,

one can try to change processor.

~igor