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    <title>i.MX ProcessorsのトピックRe: LPDDR2 pin swapping on i.MX6DL, can or not?</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-pin-swapping-on-i-MX6DL-can-or-not/m-p/414788#M62196</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Elliot&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I think if Mode Reg Read is not used, then swapping&lt;/P&gt;&lt;P&gt;can be used, as described on link.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;~igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 30 Sep 2015 07:48:51 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2015-09-30T07:48:51Z</dc:date>
    <item>
      <title>LPDDR2 pin swapping on i.MX6DL, can or not?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-pin-swapping-on-i-MX6DL-can-or-not/m-p/414783#M62191</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;I would like to use e.MCP(Kingston 08EMCP08-NL2CV100-C50) which is e.MMC 8GB + LPDDR2 8Gbit on our i.MX platform .&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;In order to do easy pcb routing,&amp;nbsp; can I swap data bus?&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;I have checked this topic :&lt;A href="https://community.nxp.com/message/410343"&gt;LPDDR2 pin swapping on iMx6DL&lt;/A&gt;&amp;nbsp; he's answer is NO, but I found another reference design which is MX6QCPULPDDR2, They do swap data bus&amp;nbsp;&amp;nbsp; .I don't know who is correct..&amp;nbsp; &lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="LPDDR2.JPG"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/58545i2FBD143E79DC00DD/image-size/large?v=v2&amp;amp;px=999" role="button" title="LPDDR2.JPG" alt="LPDDR2.JPG" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;Could anyone help me?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;Thanks,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 27 Sep 2015 05:39:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-pin-swapping-on-i-MX6DL-can-or-not/m-p/414783#M62191</guid>
      <dc:creator>elliottyang</dc:creator>
      <dc:date>2015-09-27T05:39:19Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR2 pin swapping on i.MX6DL, can or not?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-pin-swapping-on-i-MX6DL-can-or-not/m-p/414784#M62192</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Elliot&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;answer on topic was based on &lt;/SPAN&gt;&lt;A class="jive-link-external-small" href="http://www.jedec.org/sites/default/files/docs/JESD209-2B.pdf" rel="nofollow"&gt;http://www.jedec.org/sites/default/files/docs/JESD209-2B.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;and implies usage LPDDR2 memory subsystem that includes both NVM and SDRAM memories,&lt;/P&gt;&lt;P&gt;as mentioned in Annex B "LPDDR2-NVM Boot Procedure" :&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Because LPDDR2 devices (both DRAM and NVM) assign specific&lt;/P&gt;&lt;P&gt;functions to the different byte lanes of the data bus and even to specific bits within the &lt;/P&gt;&lt;P&gt;bytes, byte and bit swapping shall be avoided.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If this is only LPDRR2 chip, as in MX6QCPULPDDR2 reference design, seems&lt;/P&gt;&lt;P&gt;no problem with swapping.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 28 Sep 2015 01:42:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-pin-swapping-on-i-MX6DL-can-or-not/m-p/414784#M62192</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-09-28T01:42:23Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR2 pin swapping on i.MX6DL, can or not?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-pin-swapping-on-i-MX6DL-can-or-not/m-p/414785#M62193</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi igor&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;According to your document, I saw a note from page 9:&lt;/P&gt;&lt;P&gt;"NOTE 2 Ordering of DQ bits shall be maintained in the system, including within the package and on the PCB. DQ byte swapping and DQ bit Swapping are not allowed in the system."&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;That means DQ can't be swapped, right?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So I can't do this? JUST swap DQ BYTE.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="lpddr.JPG"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/58171i65C6767811665457/image-size/large?v=v2&amp;amp;px=999" role="button" title="lpddr.JPG" alt="lpddr.JPG" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Elliott&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 28 Sep 2015 07:33:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-pin-swapping-on-i-MX6DL-can-or-not/m-p/414785#M62193</guid>
      <dc:creator>elliottyang</dc:creator>
      <dc:date>2015-09-28T07:33:17Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR2 pin swapping on i.MX6DL, can or not?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-pin-swapping-on-i-MX6DL-can-or-not/m-p/414786#M62194</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Elliot&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;you are right, strictly following jedec this is prohibited.&lt;/P&gt;&lt;P&gt;Also it may be useful to look at&lt;/P&gt;&lt;P&gt;&lt;A href="https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/Zynq-LPDDR2-DQ-Swap-Question/td-p/396867" title="https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/Zynq-LPDDR2-DQ-Swap-Question/td-p/396867"&gt;Zynq LPDDR2 DQ Swap Question - Community Forums&lt;/A&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 28 Sep 2015 08:06:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-pin-swapping-on-i-MX6DL-can-or-not/m-p/414786#M62194</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-09-28T08:06:26Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR2 pin swapping on i.MX6DL, can or not?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-pin-swapping-on-i-MX6DL-can-or-not/m-p/414787#M62195</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi igor&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for you reply, &lt;/P&gt;&lt;P&gt;but the i.MX6DL can't set the DQ bus by software(uboot/kernel)?&lt;/P&gt;&lt;P&gt;PCB layout is so hard for implement without DQ bus changing .&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Elliott&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 30 Sep 2015 05:55:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-pin-swapping-on-i-MX6DL-can-or-not/m-p/414787#M62195</guid>
      <dc:creator>elliottyang</dc:creator>
      <dc:date>2015-09-30T05:55:24Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR2 pin swapping on i.MX6DL, can or not?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-pin-swapping-on-i-MX6DL-can-or-not/m-p/414788#M62196</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Elliot&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I think if Mode Reg Read is not used, then swapping&lt;/P&gt;&lt;P&gt;can be used, as described on link.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;~igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 30 Sep 2015 07:48:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR2-pin-swapping-on-i-MX6DL-can-or-not/m-p/414788#M62196</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-09-30T07:48:51Z</dc:date>
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