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    <title>topic About DDR3 DQS Gating, Write and Read Delay Code Example in i.MX6DQ. in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/About-DDR3-DQS-Gating-Write-and-Read-Delay-Code-Example-in-i/m-p/414433#M62120</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear All,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hello.&lt;/P&gt;&lt;P&gt;Refer to "19 DDR Calibration Code Examples" in AN4467 i.MX 6 Series DDR Calibration, Rev. 2.&lt;/P&gt;&lt;P&gt;===========&lt;/P&gt;&lt;P&gt; Code examples in this section are for 64 bit of DDR data (1 channel 64-bits DDR3, 2 channels 32-bits LPDDR2). &lt;/P&gt;&lt;P&gt;===========&lt;/P&gt;&lt;P&gt;My customer is using 1 channel 64-bits DDR3 with i.MX6DQ.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Next, refer to the below code in "19.2 DDR3 DQS Gating, Write and Read Delay Code Example".&lt;/P&gt;&lt;P&gt;===========&lt;/P&gt;&lt;P&gt;// Issue a write access to the external DDR device by setting the bit SW_DUMMY_WR (bit 0) &lt;/P&gt;&lt;P&gt;// in the MPSWDAR0 and then poll this bit until it clears to indicate completion of the write access. &lt;/P&gt;&lt;P&gt;reg32setbit((MMDC_P0_IPS_BASE_ADDR + MPSWDAR_OFFSET), 0); &lt;/P&gt;&lt;P&gt;while(reg32_read((MMDC_P0_IPS_BASE_ADDR + MPSWDAR_OFFSET)) &amp;amp; 0x00000001); &lt;/P&gt;&lt;P&gt;===========&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Finally, refer to "44.12.68 MMDC PHY SW Dummy Access Register (MMDCx_MPSWDAR0)" in IMX6DQRM(Rev.3).&lt;/P&gt;&lt;P&gt;===========&lt;/P&gt;&lt;P&gt;For Channel 0: All&lt;/P&gt;&lt;P&gt;For Channel 1: &lt;STRONG&gt;DDR3_x64&lt;/STRONG&gt;, LP2_2ch_x16, LP2_2ch_x32&lt;/P&gt;&lt;P&gt;===========&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;[Question]&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;[Q1]&lt;/P&gt;&lt;P&gt;In case of DDR3 64 bit access, is it necessary to set "SW_DUMMY_WR" for both of Channel 0 and 1?&lt;/P&gt;&lt;P&gt;(I think that it doesn't need. User should set it only for Channel 0.)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Q2]&lt;/P&gt;&lt;P&gt;I have understood as the following about MMDCx_MPSWDAR register.&lt;/P&gt;&lt;P&gt; - MMDCx_MPSWDAR[1:0] for channel 0&lt;/P&gt;&lt;P&gt; - MMDCx_MPSWDAR[5:2] for channel 0 &amp;amp; 1 : DDR3_x64&lt;/P&gt;&lt;P&gt;Is my understanding right?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Keita&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 16 Nov 2015 10:26:39 GMT</pubDate>
    <dc:creator>keitanagashima</dc:creator>
    <dc:date>2015-11-16T10:26:39Z</dc:date>
    <item>
      <title>About DDR3 DQS Gating, Write and Read Delay Code Example in i.MX6DQ.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-DDR3-DQS-Gating-Write-and-Read-Delay-Code-Example-in-i/m-p/414433#M62120</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear All,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hello.&lt;/P&gt;&lt;P&gt;Refer to "19 DDR Calibration Code Examples" in AN4467 i.MX 6 Series DDR Calibration, Rev. 2.&lt;/P&gt;&lt;P&gt;===========&lt;/P&gt;&lt;P&gt; Code examples in this section are for 64 bit of DDR data (1 channel 64-bits DDR3, 2 channels 32-bits LPDDR2). &lt;/P&gt;&lt;P&gt;===========&lt;/P&gt;&lt;P&gt;My customer is using 1 channel 64-bits DDR3 with i.MX6DQ.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Next, refer to the below code in "19.2 DDR3 DQS Gating, Write and Read Delay Code Example".&lt;/P&gt;&lt;P&gt;===========&lt;/P&gt;&lt;P&gt;// Issue a write access to the external DDR device by setting the bit SW_DUMMY_WR (bit 0) &lt;/P&gt;&lt;P&gt;// in the MPSWDAR0 and then poll this bit until it clears to indicate completion of the write access. &lt;/P&gt;&lt;P&gt;reg32setbit((MMDC_P0_IPS_BASE_ADDR + MPSWDAR_OFFSET), 0); &lt;/P&gt;&lt;P&gt;while(reg32_read((MMDC_P0_IPS_BASE_ADDR + MPSWDAR_OFFSET)) &amp;amp; 0x00000001); &lt;/P&gt;&lt;P&gt;===========&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Finally, refer to "44.12.68 MMDC PHY SW Dummy Access Register (MMDCx_MPSWDAR0)" in IMX6DQRM(Rev.3).&lt;/P&gt;&lt;P&gt;===========&lt;/P&gt;&lt;P&gt;For Channel 0: All&lt;/P&gt;&lt;P&gt;For Channel 1: &lt;STRONG&gt;DDR3_x64&lt;/STRONG&gt;, LP2_2ch_x16, LP2_2ch_x32&lt;/P&gt;&lt;P&gt;===========&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;[Question]&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;[Q1]&lt;/P&gt;&lt;P&gt;In case of DDR3 64 bit access, is it necessary to set "SW_DUMMY_WR" for both of Channel 0 and 1?&lt;/P&gt;&lt;P&gt;(I think that it doesn't need. User should set it only for Channel 0.)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[Q2]&lt;/P&gt;&lt;P&gt;I have understood as the following about MMDCx_MPSWDAR register.&lt;/P&gt;&lt;P&gt; - MMDCx_MPSWDAR[1:0] for channel 0&lt;/P&gt;&lt;P&gt; - MMDCx_MPSWDAR[5:2] for channel 0 &amp;amp; 1 : DDR3_x64&lt;/P&gt;&lt;P&gt;Is my understanding right?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Keita&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 16 Nov 2015 10:26:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-DDR3-DQS-Gating-Write-and-Read-Delay-Code-Example-in-i/m-p/414433#M62120</guid>
      <dc:creator>keitanagashima</dc:creator>
      <dc:date>2015-11-16T10:26:39Z</dc:date>
    </item>
    <item>
      <title>Re: About DDR3 DQS Gating, Write and Read Delay Code Example in i.MX6DQ.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-DDR3-DQS-Gating-Write-and-Read-Delay-Code-Example-in-i/m-p/414434#M62121</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;Keita, hi !&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;1.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; You are right, an user should set SW_DUMMY_WR only for Channel 0.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;2.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt; Control bits of MMDCx_MPSWDAR ([1:0]) affect channel 0 (64-bit) [x=0].&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;Data compare results bits of MMDCx_MPSWDAR ([5:2]) relate to corresponding &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;byte lanes [x=0,1].&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;Have a great day,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;Yuri&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 18 Nov 2015 05:32:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-DDR3-DQS-Gating-Write-and-Read-Delay-Code-Example-in-i/m-p/414434#M62121</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-11-18T05:32:39Z</dc:date>
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