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    <title>i.MX Processors中的主题 Re: i.MX25: How to read GPIO Interrupt Status Register</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX25-How-to-read-GPIO-Interrupt-Status-Register/m-p/414127#M62066</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for explaining the ISR.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The issue is, my customer claims that only a &lt;SPAN style="color: #222222; font-family: arial, sans-serif; font-size: 14px; font-style: normal; font-weight: normal; text-align: start; text-indent: 0px;"&gt;GPIO3_31 bit of IMR is set by samething.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #222222; font-family: arial, sans-serif; font-size: 14px; font-style: normal; font-weight: normal; text-align: start; text-indent: 0px;"&gt;They say they are not setting it by their software.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Do you imagine any cause by hardware, pin termination, power sequence, unstable power, etc.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Nori Shinozaki&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 17 Apr 2015 05:31:01 GMT</pubDate>
    <dc:creator>norishinozaki</dc:creator>
    <dc:date>2015-04-17T05:31:01Z</dc:date>
    <item>
      <title>i.MX25: How to read GPIO Interrupt Status Register</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX25-How-to-read-GPIO-Interrupt-Status-Register/m-p/414125#M62064</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Champs,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In the I.MX257 PDK, I breaked at 0x00000000 by JTAG and read GPIO-4 register.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;It read:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; DR&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; GDIR&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; PSR&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ICR1&lt;/P&gt;&lt;P&gt;0x53F9C000: 20000000 00000000 20000000 00000000&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ICR2&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; IMR&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;SPAN style="color: #ff0000;"&gt;ISR&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;0x53F9C010: 00000000 00000000 &lt;SPAN style="color: #ff0000;"&gt;DFFFFFFF&lt;/SPAN&gt; 00000000&lt;/P&gt;&lt;P&gt;`&lt;/P&gt;&lt;P&gt;0x20000000 in PSR means gpio4_GPIO[29] is enabled in IOMUXC.&lt;/P&gt;&lt;P&gt;The corresponding DR bit is set, because it's default direction is input and data is sensed at the pad pin.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Now in the ISR, the 29 bit looks cleard&amp;nbsp; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In Reference Manual, the default values of ISR is 0, however it looks 1 is the default/reset value.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Could you explain how to read ISR register?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Nori Shinozaki&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 16 Apr 2015 05:53:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX25-How-to-read-GPIO-Interrupt-Status-Register/m-p/414125#M62064</guid>
      <dc:creator>norishinozaki</dc:creator>
      <dc:date>2015-04-16T05:53:27Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX25: How to read GPIO Interrupt Status Register</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX25-How-to-read-GPIO-Interrupt-Status-Register/m-p/414126#M62065</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; The i.MX25 registers, in particular GPIO ones, may be changed by boot ROM,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;therefore the state of some registers may be different than stated in the Reference&lt;BR /&gt; Manual (for just after hardware reset state). Note, JTAG debugger can be connected &lt;BR /&gt; to i.MX25 only after boot ROM initializations.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; The GPIO interrupt status register (ISR) bits may be set because of corresponding&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt; &lt;SPAN style="font-size: 12.0pt; font-family: 'Verdana','sans-serif';"&gt;pin states. For example GPIO Interrupt Configuration Register(s) (ICR1, ICR2) &lt;BR /&gt;by default are configured for low-level sensitive ; that is if a pin state (DR, PSR) is 0&lt;BR /&gt;the request is set.&amp;nbsp; Note, it is not possible to reset ISR while data (DR) are zero,&lt;BR /&gt;since events will take place again. &lt;BR /&gt; &lt;BR /&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 16 Apr 2015 06:35:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX25-How-to-read-GPIO-Interrupt-Status-Register/m-p/414126#M62065</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-04-16T06:35:14Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX25: How to read GPIO Interrupt Status Register</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX25-How-to-read-GPIO-Interrupt-Status-Register/m-p/414127#M62066</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for explaining the ISR.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The issue is, my customer claims that only a &lt;SPAN style="color: #222222; font-family: arial, sans-serif; font-size: 14px; font-style: normal; font-weight: normal; text-align: start; text-indent: 0px;"&gt;GPIO3_31 bit of IMR is set by samething.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #222222; font-family: arial, sans-serif; font-size: 14px; font-style: normal; font-weight: normal; text-align: start; text-indent: 0px;"&gt;They say they are not setting it by their software.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Do you imagine any cause by hardware, pin termination, power sequence, unstable power, etc.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Nori Shinozaki&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 17 Apr 2015 05:31:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX25-How-to-read-GPIO-Interrupt-Status-Register/m-p/414127#M62066</guid>
      <dc:creator>norishinozaki</dc:creator>
      <dc:date>2015-04-17T05:31:01Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX25: How to read GPIO Interrupt Status Register</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX25-How-to-read-GPIO-Interrupt-Status-Register/m-p/414128#M62067</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;nbsp; As has been mentioned &lt;SPAN style="color: #3d3d3d; font-family: Verdana, sans-serif; font-size: 13px;"&gt;i.MX25 registers, in particular GPIO ones, may be changed by boot ROM.&lt;BR /&gt;&lt;/SPAN&gt;Is the issue reproducible on the i.MX25 PDK (without any software)?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 17 Apr 2015 05:47:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX25-How-to-read-GPIO-Interrupt-Status-Register/m-p/414128#M62067</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-04-17T05:47:11Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX25: How to read GPIO Interrupt Status Register</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX25-How-to-read-GPIO-Interrupt-Status-Register/m-p/414129#M62068</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I used i.MX257 EVK with JTAG to get the above result.&lt;/P&gt;&lt;P&gt;That is, IMRs are all 0 for each GPIOs just after out of reset.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The customer did something wrong in Software or Hardware.&lt;/P&gt;&lt;P&gt;He says he doesn't set the corresponding bit in his software.&lt;/P&gt;&lt;P&gt;Then he is asking there might be a case in hardware which set the IMR bit...&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Nori Shinozaki&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 17 Apr 2015 08:04:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX25-How-to-read-GPIO-Interrupt-Status-Register/m-p/414129#M62068</guid>
      <dc:creator>norishinozaki</dc:creator>
      <dc:date>2015-04-17T08:04:32Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX25: How to read GPIO Interrupt Status Register</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX25-How-to-read-GPIO-Interrupt-Status-Register/m-p/414130#M62069</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;nbsp; Hardly it should be a hardware to setup a mask bit : I mean normally working hardware. &lt;BR /&gt;But let's the customer to check the IMR setting without any software, on bare-metal board. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 17 Apr 2015 08:08:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX25-How-to-read-GPIO-Interrupt-Status-Register/m-p/414130#M62069</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-04-17T08:08:56Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX25: How to read GPIO Interrupt Status Register</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX25-How-to-read-GPIO-Interrupt-Status-Register/m-p/414131#M62070</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks, I've asked them if they have a JTAG connector on their board.&lt;/P&gt;&lt;P&gt;If they don't, I will ask to check with reduced software as close as bare-metal.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Nori Shinozaki&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 17 Apr 2015 08:57:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX25-How-to-read-GPIO-Interrupt-Status-Register/m-p/414131#M62070</guid>
      <dc:creator>norishinozaki</dc:creator>
      <dc:date>2015-04-17T08:57:31Z</dc:date>
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