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    <title>topic Re: i.Mx6 EIM interrupt in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-Mx6-EIM-interrupt/m-p/414118#M62061</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Peter&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes, signal called "WAIT" is the same as EIM_WAIT.&lt;/P&gt;&lt;P&gt;I can not suggest any public source of information, except&lt;/P&gt;&lt;P&gt;RM. Info about RDY_INT function was from internal ticket 1-890899012&lt;/P&gt;&lt;P&gt;provided from iMX application team.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 11 May 2015 05:16:55 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2015-05-11T05:16:55Z</dc:date>
    <item>
      <title>i.Mx6 EIM interrupt</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-Mx6-EIM-interrupt/m-p/414115#M62058</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for i.Mx6Q the reference manual states about the EIM bus "External Interrupt support, RDY_INT signal function as external interrupt". My problem is that I can not find any further information about this feature. Looking in the description about external signals I can not find any interrupt signal. I have also checked in the IO Mux Tool and can not find any interrupt pin for EIM there either.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The use-case is a i.Mx6 connected to a FPGA thorugh the EIM bus. Then it would be nice to have some interrupt from FPGA to processor. Is this possible to solve with EIM or in some other way?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;/Peter&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 08 May 2015 12:28:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-Mx6-EIM-interrupt/m-p/414115#M62058</guid>
      <dc:creator>PeterBergin</dc:creator>
      <dc:date>2015-05-08T12:28:31Z</dc:date>
    </item>
    <item>
      <title>Re: i.Mx6 EIM interrupt</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-Mx6-EIM-interrupt/m-p/414116#M62059</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Peter&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;RDY_INT function is assigned to the EIM_WAIT pin.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 09 May 2015 00:22:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-Mx6-EIM-interrupt/m-p/414116#M62059</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-05-09T00:22:01Z</dc:date>
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    <item>
      <title>Re: i.Mx6 EIM interrupt</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-Mx6-EIM-interrupt/m-p/414117#M62060</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;thanks for your reply. This was not easy to understand from the manual. A follow up question on this then, the timing diagram for "Burst (Synchronous Mode) Write Memory Access Timing - BCD=1" includes a signal called "WAIT". Is the signal WAIT in this diagram the same as EIM_WAIT?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In our project we are going to communicate between a FPGA and a i.Mx6 over the EIM bus. In general I find the documentation around EIM quite poor. Do you have any other source of information that is useful for a FPGA engineer going to implement a EIM slave?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;/Peter&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 10 May 2015 18:37:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-Mx6-EIM-interrupt/m-p/414117#M62060</guid>
      <dc:creator>PeterBergin</dc:creator>
      <dc:date>2015-05-10T18:37:37Z</dc:date>
    </item>
    <item>
      <title>Re: i.Mx6 EIM interrupt</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-Mx6-EIM-interrupt/m-p/414118#M62061</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Peter&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes, signal called "WAIT" is the same as EIM_WAIT.&lt;/P&gt;&lt;P&gt;I can not suggest any public source of information, except&lt;/P&gt;&lt;P&gt;RM. Info about RDY_INT function was from internal ticket 1-890899012&lt;/P&gt;&lt;P&gt;provided from iMX application team.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 11 May 2015 05:16:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-Mx6-EIM-interrupt/m-p/414118#M62061</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-05-11T05:16:55Z</dc:date>
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