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    <title>topic Re: i.MX6DL: external PCIe reference clock ENET implications in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6DL-external-PCIe-reference-clock-ENET-implications/m-p/413150#M61888</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I believe not, as 125MHz reference clock is provided&lt;/P&gt;&lt;P&gt;externally on ENET_REF_CLK.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 20 Jul 2015 07:34:15 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2015-07-20T07:34:15Z</dc:date>
    <item>
      <title>i.MX6DL: external PCIe reference clock ENET implications</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6DL-external-PCIe-reference-clock-ENET-implications/m-p/413147#M61885</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is anyone able to supply information regarding the impact on ENET functionality when using an external 100MHz PCIe reference clock?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The i.MX6 hardware design checklist states the following:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;"PCIe reference clock solution which provided by CLKx_N/P of i.MX6 chip can't pass PCIe Gen2 compliance test.&amp;nbsp; Recommend using external PCIe 2.0/3.0 clock generator with 2 HCSL outputs&amp;nbsp; solution. One clock channel connect to i.MX6 as a reference input, please click Ref14 for reference circuit. Another clock channel should connect to PCIe connector, please contact generator vendor for detailed design guide." &lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;There is a very useful post detailing configuration changes to support external PCIe reference clock that can be found here:&amp;nbsp; &lt;A href="https://community.nxp.com/thread/304283"&gt;i.MX6Q: Using an external reference for PCIe&lt;/A&gt;. Unfortunately, this post&amp;nbsp; doesn't address the impact this has on ethernet functionality e.g. can ethernet still be used if PLL6 is bypassed? Figure 10-3 in the DL RM seems to imply that Div_enet output will be incorrect (and can't possibly ever be 125MHz).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Grant&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jul 2015 09:50:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6DL-external-PCIe-reference-clock-ENET-implications/m-p/413147#M61885</guid>
      <dc:creator>grantfordham</dc:creator>
      <dc:date>2015-07-15T09:50:59Z</dc:date>
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    <item>
      <title>Re: i.MX6DL: external PCIe reference clock ENET implications</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6DL-external-PCIe-reference-clock-ENET-implications/m-p/413148#M61886</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Grant&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;you are right, with 100MHz bypassing, enet 125MHz can not be obtained,&lt;/P&gt;&lt;P&gt;Div_enet or CCM_ANALOG_PLL_ENET DIV_SELECT=11 - 125MHz&lt;/P&gt;&lt;P&gt;will produce 25 MHz for operating in MII mode.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 19 Jul 2015 16:17:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6DL-external-PCIe-reference-clock-ENET-implications/m-p/413148#M61886</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-07-19T16:17:33Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6DL: external PCIe reference clock ENET implications</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6DL-external-PCIe-reference-clock-ENET-implications/m-p/413149#M61887</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks for the response Igor. Can you tell me whether RGMII is affected too? I think RGMII uses external 125MHz clock on ENET_REF_CLK input (ball V22) but I'm not sure if PLL6 ENET clock is needed as well?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Grant&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 20 Jul 2015 07:25:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6DL-external-PCIe-reference-clock-ENET-implications/m-p/413149#M61887</guid>
      <dc:creator>grantfordham</dc:creator>
      <dc:date>2015-07-20T07:25:17Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6DL: external PCIe reference clock ENET implications</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6DL-external-PCIe-reference-clock-ENET-implications/m-p/413150#M61888</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I believe not, as 125MHz reference clock is provided&lt;/P&gt;&lt;P&gt;externally on ENET_REF_CLK.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 20 Jul 2015 07:34:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6DL-external-PCIe-reference-clock-ENET-implications/m-p/413150#M61888</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-07-20T07:34:15Z</dc:date>
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