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    <title>i.MX ProcessorsのトピックRe: Master clock in I2S Master mode</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Master-clock-in-I2S-Master-mode/m-p/409627#M61240</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor, thanks for the info!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I was able to do it. One thing is to know what to do and another is how to do it!&lt;/P&gt;&lt;P&gt;It's not obvious how to do it. I suppose it must to be a good place to do the&lt;/P&gt;&lt;P&gt;changes, but I'm not a Linux expert.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I've found the CLKO is linked to the 24MHz osc in clk-imx6q.c and I've&lt;/P&gt;&lt;P&gt;made some changes in that file, and now I have 33.868800MHz as SYS_MCLK,&lt;/P&gt;&lt;P&gt;useful to generate 768*fs available in the codec.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;But I think that it's not a good file choice to make the changes. Is it possible to change&lt;/P&gt;&lt;P&gt;the clock parent, divider and the rate in another file? The best option will be the DTS file,&lt;/P&gt;&lt;P&gt;but is it possible? The second option will be the ASOC machine driver file, sound/soc/fsl/imx-sta559.c.&lt;/P&gt;&lt;P&gt;The third is arch/arm/mach-imx/mach-imx6q.c and the last one, the current, clk-imx6q.c.&lt;/P&gt;&lt;P&gt;What do you think?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Any code is welcome!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 16 Apr 2015 06:00:52 GMT</pubDate>
    <dc:creator>_andev_</dc:creator>
    <dc:date>2015-04-16T06:00:52Z</dc:date>
    <item>
      <title>Master clock in I2S Master mode</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Master-clock-in-I2S-Master-mode/m-p/409625#M61238</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We have a custom board with iMX6D with the 3.10.53 linux kernel. We have connected the STA559 audio codec&lt;/P&gt;&lt;P&gt;using AUDMUX 4 for I2S interface and GPIO_0_CLKO as Master clock, like the SabreLite one. The SSI1 is configured&lt;/P&gt;&lt;P&gt;in master mode. When I play a 44.1KHz sound with aplay and I can see the signals in the scope:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;AUD4_TXC = I2S_SCLK = 2.82240MHz = 44100Hz x 2 Channels x 32 bits is OK&lt;/P&gt;&lt;P&gt;AUD4_TXD = I2S_DIN is the sound data is OK&lt;/P&gt;&lt;P&gt;AUX4_TXFS = I2S_LRCLK clock to channel left and right is OK&lt;/P&gt;&lt;P&gt;GPIO_0_CLKO = SYS_MCLK = 24MHz is NOT OK!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I know the GPIO_0_CLKO is linked to the main 24MHz OSC but we need this clock to be something like&lt;/P&gt;&lt;P&gt;576 * fs, 128 * fs, 256 * fs, 384 * fs, 512 * fs, 768 * fs, etc... where fs = 44.1KHz. Is it possible to get, for&lt;/P&gt;&lt;P&gt;example, 11.2896MHz in GPIO_0_CLK0? How???&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Apr 2015 06:11:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Master-clock-in-I2S-Master-mode/m-p/409625#M61238</guid>
      <dc:creator>_andev_</dc:creator>
      <dc:date>2015-04-15T06:11:15Z</dc:date>
    </item>
    <item>
      <title>Re: Master clock in I2S Master mode</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Master-clock-in-I2S-Master-mode/m-p/409626#M61239</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Anonymous&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;one can try to choose appropriate clock source/with divider&lt;/P&gt;&lt;P&gt;using &lt;A href="http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf?fasp=1&amp;amp;WT_TYPE=Reference%20Manuals&amp;amp;WT_VENDOR=FREESCALE&amp;amp;WT_FILE_FORMAT=pdf&amp;amp;WT_ASSET=Documentation&amp;amp;fileExt=.pdf"&gt;IMX6DQRM&lt;/A&gt; 18.6.21 CCM Clock Output Source Register (CCM_CCOSR)&lt;/P&gt;&lt;P&gt;and Figure 18-2 Clock Tree.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 16 Apr 2015 00:24:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Master-clock-in-I2S-Master-mode/m-p/409626#M61239</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-04-16T00:24:07Z</dc:date>
    </item>
    <item>
      <title>Re: Master clock in I2S Master mode</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Master-clock-in-I2S-Master-mode/m-p/409627#M61240</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor, thanks for the info!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I was able to do it. One thing is to know what to do and another is how to do it!&lt;/P&gt;&lt;P&gt;It's not obvious how to do it. I suppose it must to be a good place to do the&lt;/P&gt;&lt;P&gt;changes, but I'm not a Linux expert.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I've found the CLKO is linked to the 24MHz osc in clk-imx6q.c and I've&lt;/P&gt;&lt;P&gt;made some changes in that file, and now I have 33.868800MHz as SYS_MCLK,&lt;/P&gt;&lt;P&gt;useful to generate 768*fs available in the codec.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;But I think that it's not a good file choice to make the changes. Is it possible to change&lt;/P&gt;&lt;P&gt;the clock parent, divider and the rate in another file? The best option will be the DTS file,&lt;/P&gt;&lt;P&gt;but is it possible? The second option will be the ASOC machine driver file, sound/soc/fsl/imx-sta559.c.&lt;/P&gt;&lt;P&gt;The third is arch/arm/mach-imx/mach-imx6q.c and the last one, the current, clk-imx6q.c.&lt;/P&gt;&lt;P&gt;What do you think?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Any code is welcome!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 16 Apr 2015 06:00:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Master-clock-in-I2S-Master-mode/m-p/409627#M61240</guid>
      <dc:creator>_andev_</dc:creator>
      <dc:date>2015-04-16T06:00:52Z</dc:date>
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