topic Re: About IPU double buffer in i.MX6DQ. in i.MX Processors

About IPU double buffer in i.MX6DQ.

keitanagashima — Mon, 03 Aug 2015 04:46:32 GMT

Dear All,

Hello. I have a question about double buffer of IPU in i.MX6DQ.

My customer's system will display with double buffer mode in Non-OS program.

And, they tested the display with double buffer mode after the initialization of IPU.

[Result]

Use the Buffer0 earlier : Success

Uses the Buffer1 earlier : Looks flickering

[Question]

When one enable the Double Buffer in IPUx_CH_DB_MODE_SEL0,

Is there limitation on the 1st display?

Ex) First time, it is necessary to use from the side of Buffer0.

Best Regards,

Keita

Re: About IPU double buffer in i.MX6DQ.

Bio_TICFSL — Fri, 07 Aug 2015 14:01:46 GMT

Hi Keita,

IPU refreshes LCD in automatic way.

Please refer to sect.37.1.2.1.6 "Automatic Procedures" i.MX6DQ Reference Manual:

"..double buffering mechanism, synchronizing read and write access to system memory, to prevent tearing effects."

You can know when frame is finished using IPUx_INT_STAT registers, please refer to sect.37.5.52 "Interrupt Status Register 1 (IPUx_INT_STAT_1)"

IPUx_INT_STAT_1, End of Frame of Channel interrupt and other events.

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf

or you should check if there is no bandwidth limitation in order to see if this is the root of the flickering

Regards

Re: About IPU double buffer in i.MX6DQ.

keitanagashima — Mon, 07 Sep 2015 05:30:53 GMT

Dear Bio_TICFSL,

Hello. Sorry for my delay response.

The frame buffer was written with VSYNC interruption && "INT_STAT_1" =1.

In case of 1st writing is in both Buffer 0 and Buffer 1, the rewriting timing in the frame buffer doesn't change.

Then, flicker occurs only when the 1st writing is in Buffer1!

Have you confirm such a problem in freescale?

Best Regards,

Keita

Re: About IPU double buffer in i.MX6DQ.

karina_valencia — Wed, 28 Oct 2015 14:39:22 GMT

Re: About IPU double buffer in i.MX6DQ.

MaxTsai Oct 28, 2015 12:48 AM (in response to Jaime Hueso Zavala)

hello Keita,

My understanding is there is NO limitation for selecting IPU buffers. We just need to make sure IPU buffer being updated when DMA channel doesn't use it, and set IPU_CHA_BUFn_RDY. ipu_update_channel_buffer and ipu_select_buffer of kernel source would be reference.

For customer's flickering issue, to slow down framebuffer update and to add log to watch if IPU selects the correct buffer might be a way to debug. Customer can check if buffer 1 isn't updated well or IPU picks up incorrect buffer with that.

Regards,

Max