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    <title>i.MX ProcessorsのトピックRe: VDD_SNVS_IN Connection in SABRE Reference Design</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/VDD-SNVS-IN-Connection-in-SABRE-Reference-Design/m-p/405157#M60252</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/ko-hey"&gt;ko-hey&lt;/A&gt;​&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes, you are correct.&lt;/P&gt;&lt;P&gt;make your customer is using the latest TO chips.&lt;/P&gt;&lt;P&gt;in addition, you need to care about the other circuits which are connected to SNVS_IN.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;here is the notes in our datesheet:&lt;/P&gt;&lt;P&gt;========================================&lt;/P&gt;&lt;P&gt;2 Under normal operating conditions, the maximum current on VDD_SNVS_IN is shown Table 8. The maximum VDD_SNVS_IN&lt;/P&gt;&lt;P&gt;current may be higher depending on specific operating configurations, such as BOOT_MODE[1:0] not equal to 00, or use of&lt;/P&gt;&lt;P&gt;the Tamper feature. During initial power on, VDD_SNVS_IN can draw up to 1 mA if the supply is capable of sourcing that&lt;/P&gt;&lt;P&gt;current. If less than 1 mA is available, the VDD_SNVS_CAP charge time will increase.&lt;/P&gt;&lt;P&gt;=========================================&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 24 Sep 2015 08:06:12 GMT</pubDate>
    <dc:creator>alfred_liu</dc:creator>
    <dc:date>2015-09-24T08:06:12Z</dc:date>
    <item>
      <title>VDD_SNVS_IN Connection in SABRE Reference Design</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/VDD-SNVS-IN-Connection-in-SABRE-Reference-Design/m-p/405154#M60249</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi all&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I want to know the reason why VDD_SNVS_IN connects VSNVS_3V0 and VGEN5_2V8 in SABRE-SDB.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;According to the P2 of SDB's schematic, VDD_SNVS_IN&amp;nbsp; connects both VSNVS_3V0 and VGEN5_2V8 as below.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_0.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/57968iE8B32BA38F2D59B9/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_0.png" alt="pastedImage_0.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I think VSNVS_3V0 is enough to operate VDD_SNVS_IN.&lt;/P&gt;&lt;P&gt;Why does the VDD_SNVS_IN connect both VSNVS_3V0 and VGEN5_2V8 ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Ko-hey&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 24 Sep 2015 04:33:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/VDD-SNVS-IN-Connection-in-SABRE-Reference-Design/m-p/405154#M60249</guid>
      <dc:creator>ko-hey</dc:creator>
      <dc:date>2015-09-24T04:33:37Z</dc:date>
    </item>
    <item>
      <title>Re: VDD_SNVS_IN Connection in SABRE Reference Design</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/VDD-SNVS-IN-Connection-in-SABRE-Reference-Design/m-p/405155#M60250</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, Ko-hey&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;this is to ensure the volatge of VDD_SNVS doesn't not drop too low.&lt;/P&gt;&lt;P&gt;the reference schematic is for early TO chips, when powering up, some chips may consume current up to 1mA on SNVS_IN , which exceeds the output capacitor of Pfuse100 (400uA). &lt;/P&gt;&lt;P&gt;latest TO has fixed the issue, we didn't see the voltage drop on customer's boards till now.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;you can remove the diode on your board, or you can remain it and DNP it by default.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 24 Sep 2015 07:21:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/VDD-SNVS-IN-Connection-in-SABRE-Reference-Design/m-p/405155#M60250</guid>
      <dc:creator>alfred_liu</dc:creator>
      <dc:date>2015-09-24T07:21:56Z</dc:date>
    </item>
    <item>
      <title>Re: VDD_SNVS_IN Connection in SABRE Reference Design</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/VDD-SNVS-IN-Connection-in-SABRE-Reference-Design/m-p/405156#M60251</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;P&gt;&lt;SPAN lang="EN-US" style="FONT-SIZE: 10pt; mso-bidi-font-size: 11.0pt;"&gt;Hi &lt;/SPAN&gt;&lt;SPAN lang="EN-US" style="FONT-SIZE: 10pt; mso-ascii-font-family: Arial; mso-hansi-font-family: Arial; mso-bidi-font-family: Arial; mso-bidi-font-weight: bold;"&gt;&lt;A _jive_internal="true" href="https://community.nxp.com/people/Alfred1z"&gt;&lt;SPAN style="COLOR: windowtext; TEXT-DECORATION: none; text-underline: none;"&gt;Weisong Liu&lt;/SPAN&gt;&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="EN-US" style="FONT-SIZE: 10pt; mso-ascii-font-family: Arial; mso-hansi-font-family: Arial; mso-bidi-font-family: Arial; mso-bidi-font-weight: bold;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="EN-US" style="FONT-SIZE: 10pt; mso-ascii-font-family: Arial; mso-hansi-font-family: Arial; mso-bidi-font-family: Arial; mso-bidi-font-weight: bold;"&gt;So we need to connect only VSNVS_3V0.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="EN-US" style="FONT-SIZE: 10pt; mso-ascii-font-family: Arial; mso-hansi-font-family: Arial; mso-bidi-font-family: Arial; mso-bidi-font-weight: bold;"&gt;Is it correct ?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="EN-US" style="FONT-SIZE: 10pt; mso-ascii-font-family: Arial; mso-hansi-font-family: Arial; mso-bidi-font-family: Arial; mso-bidi-font-weight: bold;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN lang="EN-US" style="FONT-SIZE: 10pt; mso-ascii-font-family: Arial; mso-hansi-font-family: Arial; mso-bidi-font-family: Arial; mso-bidi-font-weight: bold;"&gt;Ko&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN lang="EN-US" style="FONT-SIZE: 10pt; mso-ascii-font-family: Arial; mso-hansi-font-family: Arial; mso-bidi-font-family: Arial; mso-bidi-font-weight: bold;"&gt;-hey&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="EN-US" style="FONT-SIZE: 10pt; mso-bidi-font-size: 11.0pt;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 24 Sep 2015 07:36:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/VDD-SNVS-IN-Connection-in-SABRE-Reference-Design/m-p/405156#M60251</guid>
      <dc:creator>ko-hey</dc:creator>
      <dc:date>2015-09-24T07:36:10Z</dc:date>
    </item>
    <item>
      <title>Re: VDD_SNVS_IN Connection in SABRE Reference Design</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/VDD-SNVS-IN-Connection-in-SABRE-Reference-Design/m-p/405157#M60252</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/ko-hey"&gt;ko-hey&lt;/A&gt;​&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes, you are correct.&lt;/P&gt;&lt;P&gt;make your customer is using the latest TO chips.&lt;/P&gt;&lt;P&gt;in addition, you need to care about the other circuits which are connected to SNVS_IN.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;here is the notes in our datesheet:&lt;/P&gt;&lt;P&gt;========================================&lt;/P&gt;&lt;P&gt;2 Under normal operating conditions, the maximum current on VDD_SNVS_IN is shown Table 8. The maximum VDD_SNVS_IN&lt;/P&gt;&lt;P&gt;current may be higher depending on specific operating configurations, such as BOOT_MODE[1:0] not equal to 00, or use of&lt;/P&gt;&lt;P&gt;the Tamper feature. During initial power on, VDD_SNVS_IN can draw up to 1 mA if the supply is capable of sourcing that&lt;/P&gt;&lt;P&gt;current. If less than 1 mA is available, the VDD_SNVS_CAP charge time will increase.&lt;/P&gt;&lt;P&gt;=========================================&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 24 Sep 2015 08:06:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/VDD-SNVS-IN-Connection-in-SABRE-Reference-Design/m-p/405157#M60252</guid>
      <dc:creator>alfred_liu</dc:creator>
      <dc:date>2015-09-24T08:06:12Z</dc:date>
    </item>
    <item>
      <title>Re: VDD_SNVS_IN Connection in SABRE Reference Design</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/VDD-SNVS-IN-Connection-in-SABRE-Reference-Design/m-p/405158#M60253</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;P&gt;&lt;SPAN lang="EN-US" style="font-size: 10pt; mso-bidi-font-size: 11.0pt;"&gt;Hi &lt;STRONG&gt;&lt;A _jive_internal="true" data-avatarid="-1" data-content-finding="Community" data-userid="203164" data-username="Alfred1z" href="https://community.nxp.com/people/Alfred1z"&gt;Weisong Liu&lt;/A&gt;&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Let me confirm one more thing.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The TO chips that you mentioned is i.MX6.&lt;/P&gt;&lt;P&gt;Is it correct ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="EN-US" style="font-size: 10pt; mso-bidi-font-size: 11.0pt;"&gt;Ko-hey&lt;/SPAN&gt;&lt;/P&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 24 Sep 2015 08:07:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/VDD-SNVS-IN-Connection-in-SABRE-Reference-Design/m-p/405158#M60253</guid>
      <dc:creator>ko-hey</dc:creator>
      <dc:date>2015-09-24T08:07:16Z</dc:date>
    </item>
    <item>
      <title>Re: VDD_SNVS_IN Connection in SABRE Reference Design</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/VDD-SNVS-IN-Connection-in-SABRE-Reference-Design/m-p/405159#M60254</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/ko-hey"&gt;ko-hey&lt;/A&gt;​&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes, sure for imx6.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 25 Sep 2015 07:29:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/VDD-SNVS-IN-Connection-in-SABRE-Reference-Design/m-p/405159#M60254</guid>
      <dc:creator>alfred_liu</dc:creator>
      <dc:date>2015-09-25T07:29:46Z</dc:date>
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