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    <title>topic Re: GPIO Line - Wakeup - Level Trigger in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/GPIO-Line-Wakeup-Level-Trigger/m-p/404961#M60213</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The interrupt-cells property is already configured for the GPIO contoller's output pins, and yet no expected results.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So we resorted to using the SYSFS way again. &lt;SPAN style="color: #1f497d;"&gt;So we made a try as to somehow use the existing platform code which is available for level triggering (in gpio-mxc.c, gpio_set_irq_type()) through gpliolib by routing the code flow of edge configuration (i.e. /sys/class/gpio/&amp;lt;gpionum&amp;gt;/edge) to the level trigger configuration code flow.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;OL style="list-style-type: lower-roman;"&gt;&lt;LI&gt;&lt;SPAN style="color: #1f497d;"&gt;i.e. the below code is getting executed every time before the system goes to suspend mode so that the GPIO line would act as wake input:&lt;/SPAN&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;gpio_set_irq_type()&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;{&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;switch (type) {&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;case IRQ_TYPE_EDGE_RISIN&lt;/STRONG&gt;G:&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;//edge = GPIO_INT_RISE_EDGE;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;edge = GPIO_INT_LOW_LEV;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;…&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;…&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;if (edge != GPIO_INT_BOTH_EDGES) {&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt; reg += GPIO_ICR1 + ((gpio_idx &amp;amp; 0x10) &amp;gt;&amp;gt; 2); /* lower or upper register */&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt; bit = gpio_idx &amp;amp; 0xf;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt; val = readl(reg) &amp;amp; ~(0x3 &amp;lt;&amp;lt; (bit &amp;lt;&amp;lt; 1));&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt; writel(val | (edge &amp;lt;&amp;lt; (bit &amp;lt;&amp;lt; 1)), reg);&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt; }&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt; writel(1 &amp;lt;&amp;lt; gpio_idx, port-&amp;gt;base + GPIO_ISR);&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt; return 0;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;}&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Now level triggering works but the problem is that the ISR (mxc_gpio_irq_handler) runs repeatedly as a tight loop so long as the level is there so other things are getting affected badly and the system become unusable.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Could you please give us guidance as to how to make this level triggering feature usable? &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please help. Thanks.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-&lt;/P&gt;&lt;P&gt;Ayana&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 18 Aug 2015 14:22:11 GMT</pubDate>
    <dc:creator>ayanavincent</dc:creator>
    <dc:date>2015-08-18T14:22:11Z</dc:date>
    <item>
      <title>GPIO Line - Wakeup - Level Trigger</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/GPIO-Line-Wakeup-Level-Trigger/m-p/404959#M60211</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are using custom board based on IMX6Q. We use Linux kernel imx_3.10.17_1.0.1_ga.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &lt;SPAN style="font-size: 11.0pt; font-family: 'Calibri','sans-serif';"&gt;We want to configure the 18th pin of GPIO bank 3 as wake input&amp;nbsp; in order to wake from suspend-to-RAM. Initially we chose edge triggered and we were able to do it (via SYSFS) and everything works fine. Now it turns out that we need to configure it as level triggered. The platform code has support for this (gpio_set_irq_type () in gpio-mxc.c). However, as we use gpiolib, we could only see the file, “edge”, in the SYSFS (/sys/class/gpio/gpio82/edge) and the possible values are “none”, “falling”, “rising” and “both” (gpiolib.c).&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; font-family: 'Calibri','sans-serif';"&gt; Could you please help us configure the GPIO line level trigger capable? &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; font-family: 'Calibri','sans-serif';"&gt;Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; font-family: 'Calibri','sans-serif';"&gt;Ayana Vincent&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 13 Jul 2015 12:31:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/GPIO-Line-Wakeup-Level-Trigger/m-p/404959#M60211</guid>
      <dc:creator>ayanavincent</dc:creator>
      <dc:date>2015-07-13T12:31:29Z</dc:date>
    </item>
    <item>
      <title>Re: GPIO Line - Wakeup - Level Trigger</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/GPIO-Line-Wakeup-Level-Trigger/m-p/404960#M60212</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi ayana&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;one can try to set&lt;/P&gt;&lt;P&gt;interrupt-cells property as 8 = active low level-sensitive&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/310091"&gt;Configure GPIO as interrupt source&lt;/A&gt; &lt;/P&gt;&lt;P&gt;&lt;A href="http://www.mjmwired.net/kernel/Documentation/gpio.txt#634" title="http://www.mjmwired.net/kernel/Documentation/gpio.txt#634"&gt;Linux Kernel Documentation :: gpio.txt&lt;/A&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 14 Jul 2015 01:38:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/GPIO-Line-Wakeup-Level-Trigger/m-p/404960#M60212</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-07-14T01:38:47Z</dc:date>
    </item>
    <item>
      <title>Re: GPIO Line - Wakeup - Level Trigger</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/GPIO-Line-Wakeup-Level-Trigger/m-p/404961#M60213</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The interrupt-cells property is already configured for the GPIO contoller's output pins, and yet no expected results.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So we resorted to using the SYSFS way again. &lt;SPAN style="color: #1f497d;"&gt;So we made a try as to somehow use the existing platform code which is available for level triggering (in gpio-mxc.c, gpio_set_irq_type()) through gpliolib by routing the code flow of edge configuration (i.e. /sys/class/gpio/&amp;lt;gpionum&amp;gt;/edge) to the level trigger configuration code flow.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;OL style="list-style-type: lower-roman;"&gt;&lt;LI&gt;&lt;SPAN style="color: #1f497d;"&gt;i.e. the below code is getting executed every time before the system goes to suspend mode so that the GPIO line would act as wake input:&lt;/SPAN&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;gpio_set_irq_type()&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;{&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;switch (type) {&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;case IRQ_TYPE_EDGE_RISIN&lt;/STRONG&gt;G:&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;//edge = GPIO_INT_RISE_EDGE;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;edge = GPIO_INT_LOW_LEV;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;…&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;…&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;if (edge != GPIO_INT_BOTH_EDGES) {&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt; reg += GPIO_ICR1 + ((gpio_idx &amp;amp; 0x10) &amp;gt;&amp;gt; 2); /* lower or upper register */&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt; bit = gpio_idx &amp;amp; 0xf;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt; val = readl(reg) &amp;amp; ~(0x3 &amp;lt;&amp;lt; (bit &amp;lt;&amp;lt; 1));&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt; writel(val | (edge &amp;lt;&amp;lt; (bit &amp;lt;&amp;lt; 1)), reg);&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt; }&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt; writel(1 &amp;lt;&amp;lt; gpio_idx, port-&amp;gt;base + GPIO_ISR);&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt; return 0;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;}&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Now level triggering works but the problem is that the ISR (mxc_gpio_irq_handler) runs repeatedly as a tight loop so long as the level is there so other things are getting affected badly and the system become unusable.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Could you please give us guidance as to how to make this level triggering feature usable? &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please help. Thanks.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-&lt;/P&gt;&lt;P&gt;Ayana&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 18 Aug 2015 14:22:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/GPIO-Line-Wakeup-Level-Trigger/m-p/404961#M60213</guid>
      <dc:creator>ayanavincent</dc:creator>
      <dc:date>2015-08-18T14:22:11Z</dc:date>
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