topic Re: IMX6: IPU DI chipselect signals in i.MX Processors

IMX6: IPU DI chipselect signals

ensc — Wed, 23 Sep 2015 17:42:30 GMT

Hello,

how can I control the IPU DI chipselect signals?

Reference Manual lists two chipselects for each of both display interfaces:

IPU1_DI0_D0_CS and IPU1_DI0_D1_CS for DI0
IPU1_DI1_D0_CS and IPU1_DI1_D1_CS for DI1

Do they correspond to the PROG_DISP_ID field in IPUx_DC_WR_CH_CONF_y which mentions four displays (display #0 till #3). How are they mapped in this case (e.g. does "IPU1_DI0_D0_CS" corresponds to display #0 and IPU1_DI1_D1_CS for DI1 to #3)?

Will it be possible to control a display using IPU1_DISP0_DATx pins with IPU1_DI0_D1_CS?

Re: IMX6: IPU DI chipselect signals

igorpadykov — Thu, 24 Sep 2015 02:29:11 GMT

Hi Enrico

IPUx_DIy_Dz_CS are used for asynchronous LCDs which are not

supported (no example drivers) for i.MX6 IPU.

From i.MX6DQ Reference Manual (rev.2 7/2014)

sect.37.4.10.4 Waveform settings for asynchronous interface pins :

The DI provides 8 signals that are used for asynchronous interface. These signals are

PIN11 through PIN17 (ipp_di_#_pin_11 through ipp_di_0_pin_17) and the CS

(ipp_di_0_do_dispb_d0_cs).

In general programming procedure using waveform generators is given on

Re: i.MX53: How to move VGA external HSYNC and VSYNC signals to different pins?

It is possible to control IPU1_DISP0_DATx pins with IPU1_DI0_D1_CS.

IPUx_DC_WR_CH_CONF and other DC registers are used for synchronous LCDs

as described in sect.37.4.7 DC - Display Controller

Best regards

igor

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Re: IMX6: IPU DI chipselect signals

ensc — Thu, 24 Sep 2015 10:13:28 GMT

IPUx_DIy_Dz_CS are used for asynchronous LCDs

Hi igorpadykov,

I know that these signals are for asynchronous LCDs and that no drivers are existing for them yet :smileywink:

Due to these missing drivers and an (imo) thin documentation, it is unclear to me how the CS signals are to be used.

which are not supported (no example drivers) for i.MX6 IPU.

Does this mean that asynchronous displays are not supported at all by the silicon? Or does silicon can handle them but drivers (and official support) are not existing (yet)?

It is possible to control IPU1_DISP0_DATx pins with IPU1_DI0_D1_CS.
IPUx_DC_WR_CH_CONF and other DC registers are used for synchronous LCDs
as described in sect.37.4.7 DC - Display Controller

Section 37.4.10.4 "Waveform settings for asynchronous interface pins" describes how to use them for asynchronous displays. But it speaks about one CS only; how can I control which CS out of DIx_D0_CS and DIx_D1_CS is used?

Re: IMX6: IPU DI chipselect signals

igorpadykov — Thu, 24 Sep 2015 11:43:00 GMT

Hi Enrico

I think silicon can handle them but they were not tested, no drivers

are available.

For usage DIx_D0_CS one can look at i.MX53 example of waveform generators.

Reagrding "how can I control which CS out of DIx_D0_CS and DIx_D1_CS is used"

one can look at sect.37.4.10.3.1 Waveform concatenation :

The DI provides the ability to derive the waveform from the fundamental timebase or

from another PIN. In that case, one pin's waveform is used as another pin's timebase.

Best regards

igor

Re: IMX6: IPU DI chipselect signals

ensc — Fri, 02 Oct 2015 18:10:38 GMT

how can I control the IPU DI chipselect signals?

to answer my question:

Mapping between the four displays and the CS is done within IPU_DC_READ_CH_CONF[11:8]. Despite the register name, these fields apply to all DC channels.