<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic How to accelerate to read or write FPGA? in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/How-to-accelerate-to-read-or-write-FPGA/m-p/402776#M59655</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;1, Platform is i.MX280 +Linux&lt;/P&gt;&lt;P&gt;2,FPGA is connected to i.MX280 by the NAND FLASH interface &lt;/P&gt;&lt;P&gt;3, It takes 6.6us to write 32 bytes into FPGA&amp;nbsp; now.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 11 Nov 2015 03:03:20 GMT</pubDate>
    <dc:creator>chrisyao</dc:creator>
    <dc:date>2015-11-11T03:03:20Z</dc:date>
    <item>
      <title>How to accelerate to read or write FPGA?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-to-accelerate-to-read-or-write-FPGA/m-p/402776#M59655</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;1, Platform is i.MX280 +Linux&lt;/P&gt;&lt;P&gt;2,FPGA is connected to i.MX280 by the NAND FLASH interface &lt;/P&gt;&lt;P&gt;3, It takes 6.6us to write 32 bytes into FPGA&amp;nbsp; now.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Nov 2015 03:03:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-to-accelerate-to-read-or-write-FPGA/m-p/402776#M59655</guid>
      <dc:creator>chrisyao</dc:creator>
      <dc:date>2015-11-11T03:03:20Z</dc:date>
    </item>
    <item>
      <title>Re: How to accelerate to read or write FPGA?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-to-accelerate-to-read-or-write-FPGA/m-p/402777#M59656</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Yao,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; We don't have corresponding solution of using FPGA on NAND Flash interface, so I can only give you suggestions on your application:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; You can try to use DMA to transmit data between CPU and FPGA by memory to memory. As for DMA usage, you can refter to linux BSP for i.MX28, in some device drivers, DMA was used.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Weidong&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Nov 2015 07:14:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-to-accelerate-to-read-or-write-FPGA/m-p/402777#M59656</guid>
      <dc:creator>weidong_sun</dc:creator>
      <dc:date>2015-11-12T07:14:15Z</dc:date>
    </item>
  </channel>
</rss>

