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    <title>i.MX Processors中的主题 Re: i.MX53 VPU decoder output timing</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-VPU-decoder-output-timing/m-p/400271#M59040</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The VPU has an internal DSP called the BIT processor which controls the internal hardware blocks for&lt;/P&gt;&lt;P&gt;video decoder operations.&lt;/P&gt;&lt;P&gt;The BIT processor completes decoding operations on a frame-by-frame basis, which allows low level&lt;/P&gt;&lt;P&gt;independency of VPU operations to the host processor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 14 Jul 2015 08:43:04 GMT</pubDate>
    <dc:creator>joanxie</dc:creator>
    <dc:date>2015-07-14T08:43:04Z</dc:date>
    <item>
      <title>i.MX53 VPU decoder output timing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-VPU-decoder-output-timing/m-p/400270#M59039</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Chip experts,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have a quesion when i.MX53 VPU decoded data write to the frame buffer.&lt;/P&gt;&lt;P&gt;Which timing is correct?&lt;/P&gt;&lt;P&gt; a)&amp;nbsp; data wrote per each microblock decoded&lt;BR /&gt; b)&amp;nbsp; or data wrote only when whole frame decoded&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 10 Jul 2015 08:44:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX53-VPU-decoder-output-timing/m-p/400270#M59039</guid>
      <dc:creator>torus1000</dc:creator>
      <dc:date>2015-07-10T08:44:42Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX53 VPU decoder output timing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX53-VPU-decoder-output-timing/m-p/400271#M59040</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The VPU has an internal DSP called the BIT processor which controls the internal hardware blocks for&lt;/P&gt;&lt;P&gt;video decoder operations.&lt;/P&gt;&lt;P&gt;The BIT processor completes decoding operations on a frame-by-frame basis, which allows low level&lt;/P&gt;&lt;P&gt;independency of VPU operations to the host processor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 14 Jul 2015 08:43:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX53-VPU-decoder-output-timing/m-p/400271#M59040</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2015-07-14T08:43:04Z</dc:date>
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