i.MX ProcessorsのトピックHow to enable cache for i.mx6 EIM

How to enable cache for i.mx6 EIM

rinkeshpatel — Thu, 09 Jul 2015 15:48:12 GMT

We are using LDM/STM instruction(shown below) to transfer data from i.mx6 over SRAM interface but the performance is same as no LDM/STM.

asm(

"pld [%[address]]\n\t"

"vldm %[address],{q0-q7}\n\t"

"vstm %[address1]!,{q0-q7}\n\t"

://outputs

:[address]"r"(array),[address1]"r"(pusAddr16)//inputs

:"q0","q1","q2","q3","memory"//clobbers

);

Everyone says that cache should be enabled to achieve high performance using STM/LDM.

I am new to freescale and can someone guide me How to enable cache for i.mx6 EIM?

Thanks and Regards,

Rinkesh Patel

igorpadykov — Fri, 10 Jul 2015 01:24:08 GMT

Hi Rinkesh

in linux caches are already enabled, as for example code

one can look at ..sdk/core/src/armv7_cache.c

Best regards

igor

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rinkeshpatel — Fri, 10 Jul 2015 10:13:21 GMT

Hello Igore,

Thank you very much for your reply.

Regards,

Rinkesh Patel