i.MX Processors中的主题 SPI without MISO https://community.nxp.com/t5/i-MX-Processors/SPI-without-MISO/m-p/398227#M58502 <HTML><HEAD></HEAD><BODY><P>Instead of building an SPI port with MOSI and MISO lanes, is it possible to have two symmetric seperate SPI interface with only MOSI lanes between i.MX6 and an FPGA?</P></BODY></HTML> Fri, 10 Apr 2015 14:20:35 GMT mustafademirci 2015-04-10T14:20:35Z SPI without MISO https://community.nxp.com/t5/i-MX-Processors/SPI-without-MISO/m-p/398227#M58502 <HTML><HEAD></HEAD><BODY><P>Instead of building an SPI port with MOSI and MISO lanes, is it possible to have two symmetric seperate SPI interface with only MOSI lanes between i.MX6 and an FPGA?</P></BODY></HTML> Fri, 10 Apr 2015 14:20:35 GMT https://community.nxp.com/t5/i-MX-Processors/SPI-without-MISO/m-p/398227#M58502 mustafademirci 2015-04-10T14:20:35Z Re: SPI without MISO https://community.nxp.com/t5/i-MX-Processors/SPI-without-MISO/m-p/398228#M58503 <HTML><HEAD></HEAD><BODY><P>HI Mustafa</P><P></P><P>seems one can use configuration with</P><P>one interface as master, other slave.&nbsp; One can look at</P><P><A href="http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf?fasp=1&amp;WT_TYPE=Reference%20Manuals&amp;WT_VENDOR=FREESCALE&amp;WT_FILE_FORMAT=pdf&amp;WT_ASSET=Documentation&amp;fileExt=.pdf">IMX6DQRM</A>&nbsp; sect.21.1.2 Modes and Operations</P><P></P><P>Best regards</P><P>igor</P><P>-----------------------------------------------------------------------------------------------------------------------</P><P>Note: If this post answers your question, please click the Correct Answer button. Thank you!</P><P>-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Sat, 11 Apr 2015 00:57:11 GMT https://community.nxp.com/t5/i-MX-Processors/SPI-without-MISO/m-p/398228#M58503 igorpadykov 2015-04-11T00:57:11Z