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    <title>topic Re: SGTL5000 PLL startup/reconfiguration problems in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/SGTL5000-PLL-startup-reconfiguration-problems/m-p/397603#M58393</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;This seems to be the possible effect of the SGTL5000 power silicon erratum, please refer to the SGTL5000 Chip Errata document.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Artur&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 31 Jul 2015 12:04:48 GMT</pubDate>
    <dc:creator>art</dc:creator>
    <dc:date>2015-07-31T12:04:48Z</dc:date>
    <item>
      <title>SGTL5000 PLL startup/reconfiguration problems</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SGTL5000-PLL-startup-reconfiguration-problems/m-p/397602#M58392</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello everybody,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;we are have a custom board with the i.MX53 and the sgtl5000 codec. The codec MCLK is driven by the mcu's cko2 at 24.576 MHz and generates the I2S frame- and bitclock using the internal PLL.&lt;/P&gt;&lt;P&gt;The OS is linux build the the yocto freescale BSP and the kernel version is 3.0.35.&lt;/P&gt;&lt;P&gt;When I'm playing audiofiles with different samplerates ( 8, 16, 22.05 and 44.1 kHz) with aplay one after another a few time, the codec stops playing:&lt;/P&gt;&lt;P&gt;- No audio output&lt;/P&gt;&lt;P&gt;- sometimes but not always the PLL_LOCKED bit in the SGTL5000_CHIP_ANA_STATUS is not set.&lt;/P&gt;&lt;P&gt;- the frame clock is at a wrong frequency, most of the times about 7kHz&lt;/P&gt;&lt;P&gt;- the I2C communication is still working, though the MUTE bits cannot be set anymore.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Sometimes this happens directly after boot. I haven't found a way to get out of this state except for reboot/powercycle. &lt;/P&gt;&lt;P&gt;As a try I have changed the driver to first switch of the PLL, reconfigure and switch on again. Now it is happening&lt;/P&gt;&lt;P&gt;less often but still. In the manual I only found the PLL startup sequence.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Has anybody seen a similar behaviour, or is there any advise how to handle this state?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards, Jonas&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 30 Jul 2015 13:16:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SGTL5000-PLL-startup-reconfiguration-problems/m-p/397602#M58392</guid>
      <dc:creator>jonashöppner</dc:creator>
      <dc:date>2015-07-30T13:16:43Z</dc:date>
    </item>
    <item>
      <title>Re: SGTL5000 PLL startup/reconfiguration problems</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SGTL5000-PLL-startup-reconfiguration-problems/m-p/397603#M58393</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;This seems to be the possible effect of the SGTL5000 power silicon erratum, please refer to the SGTL5000 Chip Errata document.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Artur&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 31 Jul 2015 12:04:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SGTL5000-PLL-startup-reconfiguration-problems/m-p/397603#M58393</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2015-07-31T12:04:48Z</dc:date>
    </item>
    <item>
      <title>Re: SGTL5000 PLL startup/reconfiguration problems</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SGTL5000-PLL-startup-reconfiguration-problems/m-p/397604#M58394</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks, Artur, &lt;BR /&gt;&lt;SPAN&gt;but the errata &lt;/SPAN&gt;&lt;A class="jive-link-external-small" href="http://cache.freescale.com/files/analog/doc/errata/SGTL5000ER.pdf" rel="nofollow"&gt;http://cache.freescale.com/files/analog/doc/errata/SGTL5000ER.pdf&lt;/A&gt;&lt;SPAN&gt; only contains an startup problem of the VDDD.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;In the situation described in the errata, the I2C lines are held low, breakin all I2C communication on the bus. In my situation I2C is still functional.&lt;/P&gt;&lt;P&gt;Also the codec has already played audio before and stops after reconfiguration.&lt;/P&gt;&lt;P&gt;Any other Ideas?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 31 Jul 2015 13:24:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SGTL5000-PLL-startup-reconfiguration-problems/m-p/397604#M58394</guid>
      <dc:creator>jonashöppner</dc:creator>
      <dc:date>2015-07-31T13:24:31Z</dc:date>
    </item>
    <item>
      <title>Re: SGTL5000 PLL startup/reconfiguration problems</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SGTL5000-PLL-startup-reconfiguration-problems/m-p/397605#M58395</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The problem seems to be resolved by adding the correct asound.conf files to the image ( they have been missing in mine). &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 20 Aug 2015 14:55:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SGTL5000-PLL-startup-reconfiguration-problems/m-p/397605#M58395</guid>
      <dc:creator>jonashöppner</dc:creator>
      <dc:date>2015-08-20T14:55:45Z</dc:date>
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