topic Re: EPIT Timer - LR and CMP but no Event on both? in i.MX Processors

EPIT Timer - LR and CMP but no Event on both?

benhenricksen — Thu, 09 Jul 2015 11:00:37 GMT

Hi, I have an iMX6-Solo dev board running Linux 3.10.17.

I'm looking to generate a pulse wave with the EPIT timer and the event output pin. The EPIT has a load register so you can choose an overall time and a compare register so you can choose another point within this time. But it seems you can only generate an event (pin state change) on the compare matching the count, not at the zero/reload point. If you want to have an interrupt at the reload point you have to set the compare to the reload value. So what's the point of having both these registers? Am I missing something?

Currently it looks like I have to swap reload values and output mode on every interrupt to get a pulse wave. Is this what is expected?

The GPT has a 1 clock length pulse option but it is being used as the Linux system timer.

Re: EPIT Timer - LR and CMP but no Event on both?

alejandrolozan1 — Fri, 10 Jul 2015 23:28:05 GMT

Hi,

The behavior you are facing is correct:

According to the RM:

If an interrupt is required at rollover (when the counter value reaches 0x0000_0000 and the new value is loaded) then

the compare register value should be set equal to the load register value in set-and-forget

mode, or equal to 0xFFFF_FFFF in free-running mode.

Best Regards,

Alejandro

Re: EPIT Timer - LR and CMP but no Event on both?

benhenricksen — Mon, 13 Jul 2015 09:02:42 GMT

OK, thanks for confirming the operation.

I have it working generating the pulse wave by swapping reload values and output mode on every interrupt.