<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックRe: i.mx6 DualLite processor parallel Display RGB ports</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6-DualLite-processor-parallel-Display-RGB-ports/m-p/397270#M58310</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Prev&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please check sect.4.11.10.4 IPU Display Interface Signal Mapping&lt;/P&gt;&lt;P&gt;i.MX6SDL Datasheet (rev.4, 12/2014)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6SDLCEC.pdf" rel="nofollow"&gt;http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6SDLCEC.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;and sect.4.11.10.4 IPU Display Interface Signal Mapping&lt;/P&gt;&lt;P&gt;i.MX6DQ Datasheet (rev.4, 7/2015)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6DQCEC.pdf" rel="nofollow"&gt;http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6DQCEC.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 31 Jul 2015 01:33:17 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2015-07-31T01:33:17Z</dc:date>
    <item>
      <title>i.mx6 DualLite processor parallel Display RGB ports</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6-DualLite-processor-parallel-Display-RGB-ports/m-p/397269#M58309</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;Reg Display Parallel port RGB pins.&lt;/P&gt;&lt;P&gt;As per Sabre lite EVM schematics, the Parallel ports RGB pins are connected as follows&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Which port are R,G, B.?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;is it this way as shown below,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;DISP0_DAT [0-7]&amp;nbsp; is Blue&lt;/P&gt;&lt;P&gt;DISP0_DAT[8-15] is Green&lt;/P&gt;&lt;P&gt;DISP0_DAT[16-23] is Red&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is this configuration correct, am not able to find the processor datasheet&amp;nbsp; file name IMX6SDLRM.pdf&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Can you Confirm.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_0.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/55683iAC0615FEA4AE9D0E/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_0.png" alt="pastedImage_0.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/55721i526AFB09F5EA569E/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 30 Jul 2015 13:19:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6-DualLite-processor-parallel-Display-RGB-ports/m-p/397269#M58309</guid>
      <dc:creator>prev</dc:creator>
      <dc:date>2015-07-30T13:19:57Z</dc:date>
    </item>
    <item>
      <title>Re: i.mx6 DualLite processor parallel Display RGB ports</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6-DualLite-processor-parallel-Display-RGB-ports/m-p/397270#M58310</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Prev&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please check sect.4.11.10.4 IPU Display Interface Signal Mapping&lt;/P&gt;&lt;P&gt;i.MX6SDL Datasheet (rev.4, 12/2014)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6SDLCEC.pdf" rel="nofollow"&gt;http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6SDLCEC.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;and sect.4.11.10.4 IPU Display Interface Signal Mapping&lt;/P&gt;&lt;P&gt;i.MX6DQ Datasheet (rev.4, 7/2015)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6DQCEC.pdf" rel="nofollow"&gt;http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6DQCEC.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 31 Jul 2015 01:33:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6-DualLite-processor-parallel-Display-RGB-ports/m-p/397270#M58310</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-07-31T01:33:17Z</dc:date>
    </item>
  </channel>
</rss>

