topic imx6 mipi csi2 question in i.MX Processors

imx6 mipi csi2 question

ed_nash — Sun, 03 May 2015 19:18:09 GMT

What does this sequence in mxc_mipi_csi2.c: mipi_csi2_reset() do?

mipi_csi2_write(info, 0x00000001, MIPI_CSI2_PHY_TST_CTRL0);

mipi_csi2_write(info, 0x00000000, MIPI_CSI2_PHY_TST_CTRL1);

mipi_csi2_write(info, 0x00000000, MIPI_CSI2_PHY_TST_CTRL0);

mipi_csi2_write(info, 0x00000002, MIPI_CSI2_PHY_TST_CTRL0);

mipi_csi2_write(info, 0x00010044, MIPI_CSI2_PHY_TST_CTRL1);

mipi_csi2_write(info, 0x00000000, MIPI_CSI2_PHY_TST_CTRL0);

mipi_csi2_write(info, 0x00000014, MIPI_CSI2_PHY_TST_CTRL1);

mipi_csi2_write(info, 0x00000002, MIPI_CSI2_PHY_TST_CTRL0);

mipi_csi2_write(info, 0x00000000, MIPI_CSI2_PHY_TST_CTRL0);

According to the TRM sections 40.6.13 and 40.6.14, these registers are for moving test data in and out of the bus. But in this postGetting an 'err_id_vc0' error on iMX6 MIPI-CSI it seems to have something to do with clock settings?

Thanks, Ed

Re: imx6 mipi csi2 question

Yuri — Mon, 04 May 2015 05:12:19 GMT

The stage of D-PHY initialization includes an access the D-PHY programming interface
to initialize and program the D-PHY according to the selected operating mode of the D-PHY.
This is D-PHY dependent, and this programming should be carried out according to the DPHY
databook. Sorry, there is no detailed information about programming internal MIPI CSI-2

DPHY registers, that may be done via the MIPI_CSI_PHY_TST_CTRL0/1 registers.
Some descriptions may be found regarding corresponding test registers of MIPI DSI DPHY.
Please take a look at section 41.5.1 (DSI and D-PHY initialization sequence) of the i.MX6 DQ RM.
An example also may be found in C-function "mipi_csi2_controller_program" from the Platform
SDK.

Have a great day,
Yuri

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Re: imx6 mipi csi2 question

ed_nash — Thu, 07 May 2015 02:36:57 GMT

Thanks for the insight. Is the information available under NDA - assuming it exists?