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    <title>topic Re: About active frame of IPU in i.MX6DQ. in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/About-active-frame-of-IPU-in-i-MX6DQ/m-p/396164#M58068</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Timings for frames B and C are not the same. This is reflected&amp;nbsp; in the RM.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 10 Jul 2015 09:00:14 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2015-07-10T09:00:14Z</dc:date>
    <item>
      <title>About active frame of IPU in i.MX6DQ.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-active-frame-of-IPU-in-i-MX6DQ/m-p/396161#M58065</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear All,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hello.&lt;/P&gt;&lt;P&gt;Refer to Figure 37-16. Sensor Image Frames in IMX6DQRM(Rev.2).&lt;/P&gt;&lt;P&gt;I think that Frame B and Frame C are same meaning.&lt;/P&gt;&lt;P&gt;What is difference of Frame B and C?&lt;/P&gt;&lt;P&gt;(I couldn't find the skip setting like skipped rows and skipped columns between Frame B and C.)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Keita&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 09 Jul 2015 08:05:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-active-frame-of-IPU-in-i-MX6DQ/m-p/396161#M58065</guid>
      <dc:creator>keitanagashima</dc:creator>
      <dc:date>2015-07-09T08:05:33Z</dc:date>
    </item>
    <item>
      <title>Re: About active frame of IPU in i.MX6DQ.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-active-frame-of-IPU-in-i-MX6DQ/m-p/396162#M58066</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt; From the RM : “The virtual frame A starts with the VSYNC&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;signal. After vertical blanking starts frame B. The HSYNC &lt;BR /&gt;signal indicates boundaries of the frame B. The frame B includes &lt;BR /&gt;both the active sensor frame C and horizontal blanking intervals”.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; So, difference between frame B and frame C is horizontal blanking &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;interval. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 09 Jul 2015 09:57:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-active-frame-of-IPU-in-i-MX6DQ/m-p/396162#M58066</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-07-09T09:57:18Z</dc:date>
    </item>
    <item>
      <title>Re: About active frame of IPU in i.MX6DQ.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-active-frame-of-IPU-in-i-MX6DQ/m-p/396163#M58067</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hello. Thank you for your reply.&lt;/P&gt;&lt;P&gt;My understanding was HSYNC must set low for horizontal blanking intervals from below community.&lt;/P&gt;&lt;P&gt;&lt;A _jive_internal="true" href="https://community.nxp.com/message/483801?et=watches.email.thread#483801" title="https://community.freescale.com/message/483801?et=watches.email.thread#483801"&gt;https://community.freescale.com/message/483801?et=watches.email.thread#483801&lt;/A&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So, I considered that the HSYNC signal indication (frame B) is same as Frame C.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Keita&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 09 Jul 2015 10:49:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-active-frame-of-IPU-in-i-MX6DQ/m-p/396163#M58067</guid>
      <dc:creator>keitanagashima</dc:creator>
      <dc:date>2015-07-09T10:49:09Z</dc:date>
    </item>
    <item>
      <title>Re: About active frame of IPU in i.MX6DQ.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-active-frame-of-IPU-in-i-MX6DQ/m-p/396164#M58068</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Timings for frames B and C are not the same. This is reflected&amp;nbsp; in the RM.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 10 Jul 2015 09:00:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-active-frame-of-IPU-in-i-MX6DQ/m-p/396164#M58068</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-07-10T09:00:14Z</dc:date>
    </item>
    <item>
      <title>Re: About active frame of IPU in i.MX6DQ.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-active-frame-of-IPU-in-i-MX6DQ/m-p/396165#M58069</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hello.&lt;/P&gt;&lt;P&gt;Sorry, I couldn't understand why &lt;SPAN style="color: #51626f; font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif;"&gt;frames B and C are not the same.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;"The HSYNC signal indicates boundaries of the frame B."&lt;/P&gt;&lt;P&gt;I consider that the HSYNC signal indicates the active sensor frame C because HSYNC must set low for horizontal blanking intervals.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Keita&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 13 Jul 2015 06:48:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-active-frame-of-IPU-in-i-MX6DQ/m-p/396165#M58069</guid>
      <dc:creator>keitanagashima</dc:creator>
      <dc:date>2015-07-13T06:48:07Z</dc:date>
    </item>
    <item>
      <title>Re: About active frame of IPU in i.MX6DQ.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-active-frame-of-IPU-in-i-MX6DQ/m-p/396166#M58070</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp;&amp;nbsp; Figure 37-16 relates to general considerations, when horizontal line&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;consist of the following periods :&lt;BR /&gt; - back porch ;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;- active data ;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;- horizontal blank.&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; In some sense You are right : for situation when HSYNC is used as DE signal &lt;BR /&gt;for active data, back porch and horizontal blank periods are not defined.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;Yuri.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 14 Jul 2015 09:09:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-active-frame-of-IPU-in-i-MX6DQ/m-p/396166#M58070</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-07-14T09:09:23Z</dc:date>
    </item>
    <item>
      <title>Re: About active frame of IPU in i.MX6DQ.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-active-frame-of-IPU-in-i-MX6DQ/m-p/396167#M58071</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt; In some sense You are right : for situation when HSYNC is used as DE signal for active data, back porch and horizontal blank periods are not defined.&lt;/P&gt;&lt;P&gt;OK. Thanks Yuri.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;It's my understanding.&lt;/P&gt;&lt;P&gt;- Gated Clock mode (Not use DE signal) --&amp;gt; Frame B = Frame C&lt;/P&gt;&lt;P&gt;- Use Data Enable signal --&amp;gt; Frame B != Frame C&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Keita&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 14 Jul 2015 09:18:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-active-frame-of-IPU-in-i-MX6DQ/m-p/396167#M58071</guid>
      <dc:creator>keitanagashima</dc:creator>
      <dc:date>2015-07-14T09:18:48Z</dc:date>
    </item>
    <item>
      <title>Re: About active frame of IPU in i.MX6DQ.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-active-frame-of-IPU-in-i-MX6DQ/m-p/396168#M58072</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt; Strictly speaking, the i.MX6 Datasheet(s) does not contain (require) timing specs between&lt;/P&gt;&lt;P&gt;HSYNC, VSYNC and data, therefore&amp;nbsp; we cannot say exactly if &lt;SPAN style="color: #51626f; font-family: Verdana, sans-serif;"&gt;horizontal blank = 0&lt;BR /&gt;&lt;/SPAN&gt;for the gated mode.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri. &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jul 2015 08:10:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-active-frame-of-IPU-in-i-MX6DQ/m-p/396168#M58072</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2015-07-15T08:10:46Z</dc:date>
    </item>
    <item>
      <title>Re: About active frame of IPU in i.MX6DQ.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-active-frame-of-IPU-in-i-MX6DQ/m-p/396169#M58073</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for your reply.&lt;/P&gt;&lt;P&gt;Let me confirm again.&lt;/P&gt;&lt;P&gt;In case of Gated Clock mode:&lt;/P&gt;&lt;P&gt;I consider that Start point of Frame B is same one of Frame C.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="Sensor Image Frames -2 (RM).png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/53773i4A2C92CF0F264EA6/image-size/large?v=v2&amp;amp;px=999" role="button" title="Sensor Image Frames -2 (RM).png" alt="Sensor Image Frames -2 (RM).png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Keita&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 17 Jul 2015 00:45:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-active-frame-of-IPU-in-i-MX6DQ/m-p/396169#M58073</guid>
      <dc:creator>keitanagashima</dc:creator>
      <dc:date>2015-07-17T00:45:44Z</dc:date>
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