About IPU specification.

takashitakahash — Thu, 09 Jul 2015 09:06:04 GMT

Hi community.

Our customer has 6 questions.

Would you please advice to me.

1, IPU is can ensure maximum 4Plane in DRAM.

Is it correct understanding?

2,Two IPU block with the maximum 2plane each?

Each Plane can have System Memmory 2 Plane?

Or , 1Plane to the System Memory, as 1Plane to the output of the VDIC, also have a total 2Plane?

3,If each Plane will ultimately out put from DI,

Is DI (DP?) synchronize LCD pixel clocks each Plane from the picture data, each block processes and synthesis done within one frame?

4,If each Plane will ultimately out put from DI,

When the DI is to transfer a picture of each Plane according to the drawing period of the LCD,

That way drawn(like some noise issues) to each Plane pictures may appear on the LCD?

5,IMX6DQ REF Manual of 37.1.2.1.5.1 De-interlacing in the VDIC, Output: progressive frame Rate: up to 240 MP/sec

but IMX6DQ RM of 37.4.11.7 VDIC Restrictions described on Maximum output pixel rate is 100 MP/s.

Pixel rate of output value is different, How do i understand?

6,IMX6DQ Ref Manual of 37.1.2.1.4.2 Display Processor (DP) is described Output: to display (through the DC), Rate: up to 240M pixels / sec ,

But There is no described Rate for the input. Please tell me the specified value of the input Rate.

Re: About IPU specification.

Yuri — Thu, 16 Jul 2015 07:04:22 GMT

Please look at my comments below.

If combining IPU functionality is meant – basically, single IPU contains three modules, capable

to combine two planes (DP, IC, VDIC). So, in general, up to six planes may be located in memory.

Another way, that really it is possible to combine up to four play (for single IPU).

Single IPU has two display ports, that may work simultaneously. According to section 37.1.2.1.2.2
(Display Interface) of the i.MX6 DQ Reference Manual :

Connecting To Display Devices

IPU allows the connectivity to multiple display devices. In particular, it

supports the following setup:

* Primary LCD display; can be smart, dumb (RAM-less) or dual-port; may use fast

serial, or the parallel interface or (through an integrated bridge) LVDS

interface.

* Second LCD display; can be smart or dumb (RAM-less); may use fast serial,

parallel or serial interface or (through an integrated bridge) LVDS interface.

Each of the above connections has independent settings - interface timing,

access template, chip-select, etc.

Simultaneous functionality of the above devices is possible in each of the

Following ways:

* Two devices can be accessed (synchronously or asynchronously) independently,

each through a different port: each using any of the available interfaces.

* Two devices can time-share asynchronous accesses through the legacy serial &

parallel interfaces, using the CS signals.

* Two devices can be accessed - synchronously or asynchronously - through the

same port, using the MIPI interface (through a HUB), each device being

identified by different ID's.

* An asynchronous access can be performed during vertical blanking intervals of

a synchronous access (screen refresh; to the same or other device).

Maximum output pixel rate of the VDIC is 100 MP/s.

D.
Input DP rate is not specified : it is assumed to meet 1080p (1920x1080) @ 60 fps

frame support.

Have a great day,
Yuri

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About IPU specification.

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