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    <title>topic Re: Processing flow in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Processing-flow/m-p/394199#M57653</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Takashi&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;only flows described in &lt;SPAN class="hps"&gt;Table 37-5 are time shared, "&lt;SPAN class="hps"&gt;another&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;Flow"&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="hps"&gt;&lt;SPAN class="hps"&gt;will not be &lt;SPAN class="hps"&gt;time shared. &lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class="hps"&gt;Also from Comments to Table 37-5:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;• Time-sharing&lt;/P&gt;&lt;P&gt;• IC can time-share tightly three flows: one VFx, one RCx and one PLx (with&lt;/P&gt;&lt;P&gt;independent processing parameters)&lt;/P&gt;&lt;P&gt;• DP can time-share one DS1 flow and a one DS2 flow (each with different&lt;/P&gt;&lt;P&gt;destinations and independent processing parameters)&lt;/P&gt;&lt;P&gt;• Direct access to display (DS4) time-shares tightly the display port with other&lt;/P&gt;&lt;P&gt;active DSx flows.&lt;/P&gt;&lt;P&gt;• Other time-sharing (between PLx flow and DS2 and DS3 flows in IRT) is frameby-&lt;/P&gt;&lt;P&gt;frame&lt;/P&gt;&lt;P&gt;• Any of the processing stages in the above flows can be skipped.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 26 May 2015 09:52:14 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2015-05-26T09:52:14Z</dc:date>
    <item>
      <title>Processing flow</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Processing-flow/m-p/394198#M57652</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi community.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Discribed on IMX6DQ RM of 37.1.2.1.4 Processing of Table 37-5. Time-Shared Data Flow through the IPU.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="hps"&gt;Defined&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;in&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;Table 37-5, DSx and PLx, VFx, RCx,&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;GFx&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;is not possible to&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;use&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;only&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;Flow&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;of&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;figure&lt;/SPAN&gt;?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; &lt;SPAN class="hps"&gt;Also&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;whether&lt;/SPAN&gt; , C&lt;SPAN class="hps"&gt;an I&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;set&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;another&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;Flow?&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 26 May 2015 04:47:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Processing-flow/m-p/394198#M57652</guid>
      <dc:creator>takashitakahash</dc:creator>
      <dc:date>2015-05-26T04:47:53Z</dc:date>
    </item>
    <item>
      <title>Re: Processing flow</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Processing-flow/m-p/394199#M57653</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Takashi&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;only flows described in &lt;SPAN class="hps"&gt;Table 37-5 are time shared, "&lt;SPAN class="hps"&gt;another&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;Flow"&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="hps"&gt;&lt;SPAN class="hps"&gt;will not be &lt;SPAN class="hps"&gt;time shared. &lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class="hps"&gt;Also from Comments to Table 37-5:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;• Time-sharing&lt;/P&gt;&lt;P&gt;• IC can time-share tightly three flows: one VFx, one RCx and one PLx (with&lt;/P&gt;&lt;P&gt;independent processing parameters)&lt;/P&gt;&lt;P&gt;• DP can time-share one DS1 flow and a one DS2 flow (each with different&lt;/P&gt;&lt;P&gt;destinations and independent processing parameters)&lt;/P&gt;&lt;P&gt;• Direct access to display (DS4) time-shares tightly the display port with other&lt;/P&gt;&lt;P&gt;active DSx flows.&lt;/P&gt;&lt;P&gt;• Other time-sharing (between PLx flow and DS2 and DS3 flows in IRT) is frameby-&lt;/P&gt;&lt;P&gt;frame&lt;/P&gt;&lt;P&gt;• Any of the processing stages in the above flows can be skipped.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 26 May 2015 09:52:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Processing-flow/m-p/394199#M57653</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2015-05-26T09:52:14Z</dc:date>
    </item>
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