topic Re: Why MMPF0100 VREFDDR startup few late? in i.MX Processors

Why MMPF0100 VREFDDR startup few late?

torus1000 — Fri, 18 Sep 2015 08:21:14 GMT

Dear Analog experts,

I'm not familiar with OP Amp.
When I measured MMPF0100/F0 PMIC output timing, most of SWx turned on just in time(Sq# x 2ms).

Why only VREF DDR output so delayed to start turn-on?

It seems to kept on low around 400us.

Can anybody help me?

Thanks

Re: Why MMPF0100 VREFDDR startup few late?

reyes — Tue, 22 Sep 2015 15:52:25 GMT

Hi,

This delay that you are seen is probably caused by a big capacitance in the layout VREFDDR line, I believe that this delay can probably be adjusted by modifying the output capacitor value on VREFDDR pin. Try using a lower value capacitor.

Have a great day,
Jose Reyes

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Re: Why MMPF0100 VREFDDR startup few late?

torus1000 — Thu, 24 Sep 2015 11:14:31 GMT

BTW

I reviewed VINREFDDR then found SW3AB supplied 1.5V to VINREFDDR.
Suppose if VINREFDDR>0.8V then mos FET goes ON, it takes 512us where slewrate set 25mV/16us.