i.MX Processorsのトピックi.MX6/Enet: CRC/FCS errors https://community.nxp.com/t5/i-MX-Processors/i-MX6-Enet-CRC-FCS-errors/m-p/390699#M56873 <HTML><HEAD></HEAD><BODY><P>Hi</P><P>I am noticed that I get FCS error while sending if TDAR is written even if it is set (100 out of 100,000 packets).</P><P>But this seems not to be the known erratum for the ENET.</P><P></P><P>I am using a i.MX6Q on a Phytec phyFlex-i.MX6Q board running non-linux, sending and receiving every 40us a packet.</P><P></P><P>I know there is a bandwidth limit (measured 600MB/s) but the FCS errors come even at a bandwidth of 200MB/s.</P><P></P><P>Did anyone experience the same?</P></BODY></HTML> Thu, 04 Dec 2014 14:49:27 GMT bastian_schick 2014-12-04T14:49:27Z i.MX6/Enet: CRC/FCS errors https://community.nxp.com/t5/i-MX-Processors/i-MX6-Enet-CRC-FCS-errors/m-p/390699#M56873 <HTML><HEAD></HEAD><BODY><P>Hi</P><P>I am noticed that I get FCS error while sending if TDAR is written even if it is set (100 out of 100,000 packets).</P><P>But this seems not to be the known erratum for the ENET.</P><P></P><P>I am using a i.MX6Q on a Phytec phyFlex-i.MX6Q board running non-linux, sending and receiving every 40us a packet.</P><P></P><P>I know there is a bandwidth limit (measured 600MB/s) but the FCS errors come even at a bandwidth of 200MB/s.</P><P></P><P>Did anyone experience the same?</P></BODY></HTML> Thu, 04 Dec 2014 14:49:27 GMT https://community.nxp.com/t5/i-MX-Processors/i-MX6-Enet-CRC-FCS-errors/m-p/390699#M56873 bastian_schick 2014-12-04T14:49:27Z Re: i.MX6/Enet: CRC/FCS errors https://community.nxp.com/t5/i-MX-Processors/i-MX6-Enet-CRC-FCS-errors/m-p/390700#M56874 <HTML><HEAD></HEAD><BODY><P>For reference: The problem wasn't TDAR or the errata, but a wrong IOMUX setup for the DDR-RAM: CMOS instead to differential on some pins. This resulted in a bit error from time to time.</P></BODY></HTML> Thu, 25 Dec 2014 16:36:17 GMT https://community.nxp.com/t5/i-MX-Processors/i-MX6-Enet-CRC-FCS-errors/m-p/390700#M56874 bastian_schick 2014-12-25T16:36:17Z