<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: i.MX and FPGA in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-and-FPGA/m-p/148186#M566</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Do you want serial or can it be parallel? For serial you could use the SATA interface. Alternatively at 32-bit parallel that is only 3.9MBps which should be do-able with the slow ROM/SRAM interface.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 01 Feb 2012 09:26:50 GMT</pubDate>
    <dc:creator>ChrisPonder</dc:creator>
    <dc:date>2012-02-01T09:26:50Z</dc:date>
    <item>
      <title>i.MX and FPGA</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-and-FPGA/m-p/148178#M558</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;SPAN&gt;I am trying to find-out the suitable link in i.MX51 to interface with FPGA at 125Mbps data speed. If anybody experienced with this type of interface, plz throw some light on this.&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 28 Dec 2010 13:48:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-and-FPGA/m-p/148178#M558</guid>
      <dc:creator>BharathiSubrama</dc:creator>
      <dc:date>2010-12-28T13:48:58Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX and FPGA</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-and-FPGA/m-p/148179#M559</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I develop a same device. My Arm connect FPGA by EMI of ARM.&lt;/P&gt;&lt;P&gt;But i used At91sam9260 not IMX...&lt;/P&gt;&lt;P&gt;You need connect FPGA to EMI of ARM used SRAM interface!&lt;/P&gt;&lt;P&gt;FPGA same SRAM momory of ARM. In ARM, you config EMI parameter at inint section of OS. In app you used mmap to communication with ARM! I hope some imformation can help you! Good lucky!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 07 Feb 2011 16:57:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-and-FPGA/m-p/148179#M559</guid>
      <dc:creator>vudinhminh</dc:creator>
      <dc:date>2011-02-07T16:57:11Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX and FPGA</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-and-FPGA/m-p/148180#M560</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks Minh. I assume EMI=EMIF. I am also moving in the same direction. By the way, Can you please share some info on raw and application level throughput&amp;nbsp;achieved in your project?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 08 Feb 2011 03:00:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-and-FPGA/m-p/148180#M560</guid>
      <dc:creator>BharathiSubrama</dc:creator>
      <dc:date>2011-02-08T03:00:19Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX and FPGA</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-and-FPGA/m-p/148181#M561</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Sory! I am a HW guy, not SW...! &lt;BR /&gt;I have'n check thoughput in my design. Becuse i don't need hight thoughphut. But i think that your thoughput you need have must used RAW fimware not application level or a solution combine driver level and application! And i think you easy to do this if you used RAW firmware in ARM and used 32 bit bus with a fast SRAM IF in FPGA. Good looky!&lt;/P&gt;&lt;P&gt;&amp;nbsp; &lt;BR /&gt; &lt;CITE&gt;Bharathi Subramanian said:&lt;/CITE&gt;&lt;/P&gt;&lt;BLOCKQUOTE cite="http://imxcommunity.org/forum/topics/imx-and-fpga?commentId=4103961%3AComment%3A4007&amp;amp;xg_source=msg_com_forum#4103961Comment4007"&gt;&lt;DIV&gt;&lt;P&gt;Thanks Minh. I assume EMI=EMIF. I am also moving in the same direction. By the way, Can you please share some info on raw and application level throughput&amp;nbsp;achieved in your project?&lt;/P&gt;&lt;/DIV&gt;&lt;/BLOCKQUOTE&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 08 Feb 2011 11:52:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-and-FPGA/m-p/148181#M561</guid>
      <dc:creator>vudinhminh</dc:creator>
      <dc:date>2011-02-08T11:52:49Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX and FPGA</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-and-FPGA/m-p/148182#M562</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Do you find any info about connect i.MX and FPGA? Can you share please?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 31 Jan 2012 07:22:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-and-FPGA/m-p/148182#M562</guid>
      <dc:creator>Max1z</dc:creator>
      <dc:date>2012-01-31T07:22:40Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX and FPGA</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-and-FPGA/m-p/148183#M563</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Starting with i.MX6 which offers PCI Express ports, we offer the Lancero PCIe SGDMA solution to achieve high bandwidth to an Altera FPGA:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="http://www.lancero.biz/" target="_blank"&gt;http://www.lancero.biz/&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;For simpler approaches, indeed attach the FPGA as an SRAM device on the external bus if it is available.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 31 Jan 2012 15:30:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-and-FPGA/m-p/148183#M563</guid>
      <dc:creator>sidebranch</dc:creator>
      <dc:date>2012-01-31T15:30:54Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX and FPGA</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-and-FPGA/m-p/148184#M564</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Other option that might be consider if you're only transferring data from FPGA to i.MX is to use the camera sensor input (CSI). This module is capable of high speed transfers and has own DMA capability (provided by IPU) for storing this data directly to memory.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 01 Feb 2012 08:16:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-and-FPGA/m-p/148184#M564</guid>
      <dc:creator>VladanJovanovic</dc:creator>
      <dc:date>2012-02-01T08:16:04Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX and FPGA</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-and-FPGA/m-p/148185#M565</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks Leon. Any benchmarking experiment done on this interface, like what is max throughput and CPU load etc ..&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 01 Feb 2012 09:23:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-and-FPGA/m-p/148185#M565</guid>
      <dc:creator>BharathiSubrama</dc:creator>
      <dc:date>2012-02-01T09:23:03Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX and FPGA</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-and-FPGA/m-p/148186#M566</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Do you want serial or can it be parallel? For serial you could use the SATA interface. Alternatively at 32-bit parallel that is only 3.9MBps which should be do-able with the slow ROM/SRAM interface.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 01 Feb 2012 09:26:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-and-FPGA/m-p/148186#M566</guid>
      <dc:creator>ChrisPonder</dc:creator>
      <dc:date>2012-02-01T09:26:50Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX and FPGA</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-and-FPGA/m-p/148187#M567</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Bharathi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;PCI Express SGDMA is ~200 MBytes/second with smallest payload, per lane. On small embedded SoCs, depending on the SoC we have measured 170 MBytes/second to 210 MBytes/second. Only few SoCs come with multiple lanes, such as the Freescale PowerPC P2022, which is a 4 lane SoC.&lt;/P&gt;&lt;P&gt;For i.MX5, if you need that kind of bandwidths to/from the FPGA, indeed you would have to (ab)use SATA or another high speed interface. i.MX6 brings PCIe connectivity.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If you need more info on Lancero specifically, contact me directly, I think this is off-topic here.&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Leon.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 01 Feb 2012 11:01:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-and-FPGA/m-p/148187#M567</guid>
      <dc:creator>sidebranch</dc:creator>
      <dc:date>2012-02-01T11:01:28Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX and FPGA</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-and-FPGA/m-p/148188#M568</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I also review interface for data trasfer from fpga. what interface do you select?&amp;nbsp; &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 02 Jun 2016 02:04:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-and-FPGA/m-p/148188#M568</guid>
      <dc:creator>hanseunglee</dc:creator>
      <dc:date>2016-06-02T02:04:30Z</dc:date>
    </item>
  </channel>
</rss>

