topic Re: i.mx6 CSI0_DATA_EN in i.MX Processors

i.mx6 CSI0_DATA_EN

allanmatthew — Thu, 28 Aug 2014 19:50:42 GMT

Is there a diagram anywhere of the timing required when using the CSI0_DATA_EN pin? The Reference Manual and i.MX6 datasheets do not show the pin in any diagram or description that I've seen.

Furthermore, is there any configuration required to enable the DATA_ENABLE pin beyond setting it in the DTB (pinctl_ipu1_2) and setting the csi_param.data_en_pol?

Thanks

Re: i.mx6 CSI0_DATA_EN

igorpadykov — Thu, 28 Aug 2014 23:38:32 GMT

Hi Allan

I am afraid such diagram is not available.

Answer on second qustion is no, in Freescale BSPs this DATA_ENABLE

signal is just set to correct value, so CSI could accept data.

Best regards

chip

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Re: i.mx6 CSI0_DATA_EN

allanmatthew — Thu, 28 Aug 2014 23:50:23 GMT

Chip- should the DE be active-high or active-low?

Re: i.mx6 CSI0_DATA_EN

igorpadykov — Fri, 29 Aug 2014 06:36:19 GMT

DE is active-high

Best regards

chip

Re: i.mx6 CSI0_DATA_EN

allanmatthew — Fri, 29 Aug 2014 14:15:38 GMT

For anyone else struggling with this, I received this diagram from FSL support: