topic HDMI Interlaced Modes in i.MX Processors

HDMI Interlaced Modes

jonchaps — Mon, 05 Jan 2015 21:24:29 GMT

Hello,

After applying the interlaced mode patches posted at Patch for iMX6 BSP to support interlaced display on HDMI and LCD interface, I've encountered issues while trying to perform HDMI compliance testing for interlaced modes. The first issue appears to be with the 4th patch. With the 4th patch applied the HDMI output will generate an invalid field every other field. It appears that one of the lines is cut short at the end of the field. Once this patch is reverted the remaining issue appears to be that the H to V offset is invalid. When operating in 1080i@60 we get an H to V value of 1101 and 1 depending on the field. These should be 1100 and 0 since the VSYNC should happen during the same clock cycle as the HSYNC. I've tried manipulating various parameters of the IPU timing generation signals but havent found a way to correct the H to V offset. Any ideas?

Thanks,

Jon

Re: HDMI Interlaced Modes

jamesbone — Thu, 08 Jan 2015 16:36:52 GMT

Hello Jon,

We are discussion your issue internally we expect to provide an update soon.

Re: HDMI Interlaced Modes

qiang_li-mpu_se — Fri, 09 Jan 2015 07:27:49 GMT

Hi Jon, we haven't checked the interlace signal by some measurement device, maybe there is still timing issue, I will check it.

Re: HDMI Interlaced Modes

qiang_li-mpu_se — Mon, 16 Mar 2015 09:30:41 GMT

The patch to fix this issue had been released in Patch for iMX6 BSP to support interlaced display on HDMI and LCD interface.

Re: HDMI Interlaced Modes

jonchaps — Fri, 03 Apr 2015 15:55:45 GMT

Hello Qiang Li,

I posted this in the patch thread already, but I'm repeating it here in case the other thread isn't being watched:

Unfortunately there still appears to be an issue. This patch doesn’t have the same issues the previous “patch 4” had, but it still has a problem where the VSYNC signal is offset by one pixel clock from where it should be. The CEA-861 specification states that the VSYNC should be perfectly aligned with the HSYNC signal plus or minus zero pixel clocks for field 1. For field 2 the VSYNC should be Htotal/2 pixel clocks from the leading edge of the HSYNC signal plus or minus zero pixel clocks. In both cases the VSYNC is 1 pixel clock too late.

Thanks,

Jon

Re: HDMI Interlaced Modes

qiang_li-mpu_se — Tue, 07 Apr 2015 02:19:37 GMT

Hi Jon, yes, there is still issue remained, I'm checking it.

Re: HDMI Interlaced Modes

qiang_li-mpu_se — Wed, 22 Apr 2015 09:58:09 GMT

I had tried many parameters, although the HDMI display can show the screen, the measured signal is still not align with CEA-861 specification, I need more time to tune it.

Re: HDMI Interlaced Modes

qiang_li-mpu_se — Wed, 13 May 2015 03:53:09 GMT

A new patch for interlaced HDMI display mode had been released at Patch for iMX6 BSP to support interlaced display on HDMI and LCD interface

From my test, it had fixed the timing issue for CEA-861-D specification.

This an automatic process. We are marking this post as s...

CommunityBot — Thu, 03 Sep 2020 16:23:46 GMT

This an automatic process.

We are marking this post as solved, due to the either low activity or any reply marked as correct.

If you have additional questions, please create a new post and reference to this closed post.

NXP Community!