topic Re: Unable to integrate a Marvell 88E6071 switch on imx28 board with MII/MDIO in i.MX Processors

Unable to integrate a Marvell 88E6071 switch on imx28 board with MII/MDIO

olivergraute — Thu, 06 Nov 2014 13:33:16 GMT

We're currently trying to communicate using MII/MDIO bus from a IMX28 CPU to a Marvell Ethernet Switch (88E6071).

We also using MDC / MDIO link to configure it from a userspace tool called mii_diag. Here we can set registers of the switch manually.

The MDC / MDIO link works well. We can see when a connection is established on a port of the switch.

But now we are trying to use the Distributed Switch Architecture of the Marvel Switch via the MDIO Bus.

From the CPU point of view, this external(DSA) Marvell device needs to be driven to take switch configuration and commands.

So we need some sort of device driver to initialise and drive the DSA chip. We found the gianfar, fsl_pq_mdio drivers In Linux Kernel Sources.

Are these drivers the right on for IMX28 MDIO_BUS Support?

How to adapt the Device Tree for MDIO_BUS Support?

We using Linux 3.9.11 Environment with gianfar fsl_pq_mdio driver.

We are using this dts to configure our switch and mdio_bus :

mdio_bus: mdio {

#address-cells = <1>;

#size-cells = <0>;

device_type = "mdio";

compatible = "fsl,gianfar-mdio";

status = "okay";

ethphy0: ethernet-phy@0 {

reg = <0>;

};

ethphy1: ethernet-phy@1 {

reg = <1>;

};

}

dsa@0 {

compatible = "marvell,dsa";

#address-cells = <2>;

#size-cells = <0>;

interrupts = <10>;

dsa,ethernet = <&mac1>;

dsa,mii-bus = <&ethphy1>;

switch@0 {

#address-cells = <1>;

#size-cells = <0>;

//reg = <16 0>; /* MDIO address 16, switch 0 in tree */

reg = <5 0>; /* MDIO address 16, switch 0 in tree */

port@0 {

reg = <0>;

label = "lan1";

phy-handle = <&ethphy1>;

};

port@1 {

reg = <1>;

label = "lan2";

};

port@2 {

reg = <2>;

label = "lan3";

};

port@3 {

reg = <3>;

label = "lan4";

};

port@4 {

reg = <4>;

label = "lan5";

};

port@5 {

reg = <5>;

label = "cpu";

};

Nachricht geändert durch Oliver Graute

Re: Unable to integrate a Marvell 88E6071 switch on imx28 board with MII/MDIO

alejandrolozan1 — Mon, 24 Nov 2014 20:40:07 GMT

Hi,

I have skimmed throug the code and files and it seems that the gianfar drivers are provided only for the mpc family. And I have not found any document or example that can be provided for reference.

Regards,

Alejandro

Re: Unable to integrate a Marvell 88E6071 switch on imx28 board with MII/MDIO

olivergraute — Tue, 25 Nov 2014 08:39:45 GMT

Ok thanks, but it seems that somebody works on a ARM port Patch for the gianfar driver. But even with this Patch is this driver the right one for probing a switch connected to a IMX28 MII/MDIO Bus?

http://permalink.gmane.org/gmane.linux.network/333411

Best Regards,

Oliver

Re: Unable to integrate a Marvell 88E6071 switch on imx28 board with MII/MDIO

jagsgediya — Fri, 12 Dec 2014 12:22:40 GMT

Hi Oliver,

Have you found any way to make marvell switch working with imx?

I am using 88e6065 with imx6. Could you please share your device tree and kernel changes?

Thanks,

Jags

Re: Unable to integrate a Marvell 88E6071 switch on imx28 board with MII/MDIO

olivergraute — Mon, 15 Dec 2014 10:46:06 GMT

Hello Jags,

unfortunately we still do not get it running. We are using the attached Device Tree Snippet and modified the mv88e6060 driver to a mv88e6071 driver (i can't publish the driver changes yet, some register setitings where different).

The Error on Kernel bootup is this one:

[ 19.800094] Distributed Switch Architecture driver version 0.1

[ 19.874578] dsa: probe of dsa.5 failed with error -22

It looks as if something with the MDIO connection to the DSA Driver is not working correclty. I'am not sure if the probing is on the "right" mdiobus on the right way I'am also not sure if we have to use the gianfar driver, the fsl-fec-mdio or the fsl,pq1-fec-mdio driver.

If you go further please tell me...

* Marvell Distributed Switch Architecture Device Tree Bindings

* A DSA node can contain multiple switch chips which are therefore child nodes of

* the parent DSA node. The maximum number of allowed child nodes is 4

dsa@0 {

compatible = "marvell,dsa";

#address-cells = <2>;

#size-cells = <0>;

interrupts = <10>;

//dsa,ethernet = <&ethphy1>;

//dsa,ethernet = <&eth1>;

dsa,ethernet = <&mac1>;

//dsa,ethernet = <&mac0>;

dsa,mii-bus = <&mdio_bus>;

switch@0 {

#address-cells = <1>;

#size-cells = <0>;

reg = <0x10 0>; /* MDIO address 16, switch 0 in tree */

//reg = <0x05 0>; /* MDIO address 16, switch 0 in tree */

port@0 {

reg = <0>;

label = "lan1";

phy-handle = <&ethphy1>;

};

port@1 {

reg = <1>;

label = "lan2";

};

port@2 {

reg = <2>;

label = "lan3";

};

mdio_bus: mdio@800f0040 {

#address-cells = <1>;

#size-cells = <0>;

device_type = "mdio";

//reg = <24520 20>;

//reg = <0xd0072004 0x4>;

//compatible = "fsl,gianfar-mdio";

//compatible = "fsl-fec-mdio";

compatible = "fsl,mpc875-fec-mdio", "fsl,pq1-fec-mdio";

//reg = <0xe00 0x188>;

reg = <0x800f0040 0x188>;

status = "okay";

ethphy0: ethernet-phy@0 {

//compatible = "fsl,gianfar-mdio";

//compatible = "fsl-fec-mdio";

compatible = "fsl,mpc875-fec-mdio", "fsl,pq1-fec-mdio";

device_type = "network";

model = "FEC";

reg = <0>;

};

ethphy1: ethernet-phy@1 {

//compatible = "fsl,gianfar-mdio";

//compatible = "fsl-fec-mdio";

compatible = "fsl,mpc875-fec-mdio", "fsl,pq1-fec-mdio";

device_type = "network";

model = "FEC";

reg = <1>;

};

//reg = <0xff>; */ /* No PHY attached */

//speed = <1000>;

//duple = <1>;

};

port@3 {

reg = <3>;

label = "lan4";

};

port@4 {

reg = <4>;

label = "lan5";

};

port@5 {

reg = <5>;

label = "cpu";

};