i.MX ProcessorsのトピックRe: DTSI file format for imx6sl

DTSI file format for imx6sl

eugenephua — Fri, 13 Mar 2015 01:47:36 GMT

Hello there, i was looking at the imx6sl.dtsi file at linux-2.6-imx.git - Freescale i.MX Linux Tree and saw the uart1 and uart4 entry. How does the fsl,pins entry come about? An example taken from the code is: MX6SL_PAD_SD1_DAT4__UART4_RX_DATA 0x1b0b1

How does the 0x1b0b1 comes about? Thanks!

Re: DTSI file format for imx6sl

Yuri — Fri, 13 Mar 2015 08:34:15 GMT

The line “MX6SL_PAD_SD1_DAT4__UART4_RX_DATA 0x1b0b1”
means : i.MX6 SL SD1_DATA4 will be configured as UART4_RX_DATA (ALT4)
and value of the Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA4)
will be init as 0x1b0b1.

Have a great day,
Yuri

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Re: DTSI file format for imx6sl

eugenephua — Sun, 15 Mar 2015 04:53:38 GMT

Hi Yuri, thanks for the great explanation. One last thing is how do i map the values 0x1b0b1 to

CONFIG bits definition: PAD_CTL_LVE (1 << 22) PAD_CTL_HYS (1 << 16) PAD_CTL_PUS_100K_DOWN (0 << 14) PAD_CTL_PUS_47K_UP (1 << 14) PAD_CTL_PUS_100K_UP (2 << 14) PAD_CTL_PUS_22K_UP (3 << 14) PAD_CTL_PUE (1 << 13) PAD_CTL_PKE (1 << 12) PAD_CTL_ODE (1 << 11) PAD_CTL_SPEED_LOW (1 << 6) PAD_CTL_SPEED_MED (2 << 6) PAD_CTL_SPEED_HIGH (3 << 6) PAD_CTL_DSE_DISABLE (0 << 3) PAD_CTL_DSE_240ohm (1 << 3) PAD_CTL_DSE_120ohm (2 << 3) PAD_CTL_DSE_80ohm (3 << 3) PAD_CTL_DSE_60ohm (4 << 3) PAD_CTL_DSE_48ohm (5 << 3) PAD_CTL_DSE_40ohm (6 << 3) PAD_CTL_DSE_34ohm (7 << 3) PAD_CTL_SRE_FAST (1 << 0)

PAD_CTL_SRE_SLOW (0 << 0)

thanks!

Re: DTSI file format for imx6sl

Yuri — Mon, 16 Mar 2015 03:03:13 GMT

According to section 30.4.335 (Pad Control Register) of the i.MX6 SL Reference
Manual,

IOMUXC_SW_PAD_CTL_PAD_SD1_DATA4 = 0x1b0b1

means :

PAD_CTL_SRE_FAST (1 << 0)

PAD_CTL_DSE_40ohm (6 << 3)

PAD_CTL_SPEED_MED (2 << 6)

PAD_CTL_PUE (1 << 13)

PAD_CTL_PKE (1 << 12)

PAD_CTL_PUS_100K_UP (2 << 14)

PAD_CTL_HYS (1 << 16)

Regards,

Yuri.