Dual camera capture

takashitakahash — Thu, 06 Nov 2014 09:05:51 GMT

I have 3 additional questions.

1, Description of IMX6SDL RM of Table 38-29.

IPU's capture flows 『Capturing interlaced input and
storing it in the memory (via VDIC) while performing video de-interlacing in
the VDIC.』 in 『Interlaced input coming from one of the CSIs is sent to the memory without processing via channel #13.

Below in my understanding is correct?

Table 38-9 listed IDMAC DMA channels list, IDMAC_CH_13 at the VDIC Source and Destination are Fmem.

However, correct in understanding that the real CH_13 at the CSI Source, Destination Fmem, en route via the VDIC, so Source listed the VDIC?

And Using a CH_13, CSI → VDIC transfer, without the IDMAC of another channel?.

2, In the VDIC, without any De-interlacing On the Fly,

That is correct understanding?

When capturing simultaneously CSI1, both CSI0 and CSI1 using IDMAC CH_13 into the via the VDIC Fmem.

And VDIC is de-interlacing at once only of 1 ch, even if can be relay to the above CSI → Fmem and will be 2ch at the same time?

3, When capturing BT.656 from CSI1, CSI0 2-channel sametime, route and IDMAC channel in the below mentioned correct?

CSI0 or 1 →VDIC (IDMAC_CH_13, De-interlacing in the On thefly),
VDIC → Fmem (IDMAC_CH_5)
CSI1 or 0 →
VDIC via → Fmem (IDMAC_CH_13), Fmem → VDIC (CH_8),
VDIC → Fmem (CH_5)

In it correct?

Re: Dual camera capture

Yuri — Fri, 07 Nov 2014 07:06:28 GMT

Please look at my comments below.

Your understanding is correct :

When using the CH_13, the next pipeline is assumed CSI -> VDIC –> (via IDMA) mem

2.
The VDIC supports a single video stream at any given time.

3.
As mentioned under item 2, the VDIC cannot be used simultaneously with two CSI inputs.

Have a great day,
Yuri

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