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    <title>i.MX ProcessorsのトピックProblem accessing the Port Logic Registers of PCIe Core when configured as RC.</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Problem-accessing-the-Port-Logic-Registers-of-PCIe-Core-when/m-p/382522#M55180</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi iMX communitiy. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are creating a PCIe driver from scratch for the i.MX 6Solo (this because we need to give PCIe support to a proprietary RTOS). So we are just starting to experiment with the PCIe Core. We were trying to initialize the PCIe core (setting the clocks and setting the core as RC Mode, however we don't have any PCIe endpoint connected yet, we are just trying to setup the core).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The problem is that we are not able to access the Port Logic Registers. When trying to access them the system crashed. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What needs to be done in order to access the Port Logic Registers?. Are these registers accesible as normal memory registers?.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your support.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 26 Aug 2014 18:45:36 GMT</pubDate>
    <dc:creator>andresgonzalez</dc:creator>
    <dc:date>2014-08-26T18:45:36Z</dc:date>
    <item>
      <title>Problem accessing the Port Logic Registers of PCIe Core when configured as RC.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Problem-accessing-the-Port-Logic-Registers-of-PCIe-Core-when/m-p/382522#M55180</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi iMX communitiy. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are creating a PCIe driver from scratch for the i.MX 6Solo (this because we need to give PCIe support to a proprietary RTOS). So we are just starting to experiment with the PCIe Core. We were trying to initialize the PCIe core (setting the clocks and setting the core as RC Mode, however we don't have any PCIe endpoint connected yet, we are just trying to setup the core).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The problem is that we are not able to access the Port Logic Registers. When trying to access them the system crashed. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What needs to be done in order to access the Port Logic Registers?. Are these registers accesible as normal memory registers?.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your support.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 26 Aug 2014 18:45:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Problem-accessing-the-Port-Logic-Registers-of-PCIe-Core-when/m-p/382522#M55180</guid>
      <dc:creator>andresgonzalez</dc:creator>
      <dc:date>2014-08-26T18:45:36Z</dc:date>
    </item>
    <item>
      <title>Re: Problem accessing the Port Logic Registers of PCIe Core when configured as RC.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Problem-accessing-the-Port-Logic-Registers-of-PCIe-Core-when/m-p/382523#M55181</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Andres&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please look at bare-metal SDK, it has PCIe example&lt;/P&gt;&lt;P&gt;(one needs to have external PCIe device connected to Sabre board)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6Q&amp;amp;nodeId=018rH3ZrDRB24A&amp;amp;fpsp=1&amp;amp;tab=Design_Tools_Tab"&gt;i.MX 6Series Platform SDK&lt;/A&gt; &lt;IMG alt="" class="jiveImage" src="http://www.freescale.com/files/graphic/SECURITYINFOIMAGE.gif" /&gt; : Bare-metal SDK&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;chip&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 27 Aug 2014 23:25:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Problem-accessing-the-Port-Logic-Registers-of-PCIe-Core-when/m-p/382523#M55181</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2014-08-27T23:25:56Z</dc:date>
    </item>
    <item>
      <title>Re: Problem accessing the Port Logic Registers of PCIe Core when configured as RC.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Problem-accessing-the-Port-Logic-Registers-of-PCIe-Core-when/m-p/382524#M55182</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks now we are able to access the Port Logic registers. We are using the Nitrogen6 Lite board. I am going to check that example. Thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 27 Aug 2014 23:34:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Problem-accessing-the-Port-Logic-Registers-of-PCIe-Core-when/m-p/382524#M55182</guid>
      <dc:creator>andresgonzalez</dc:creator>
      <dc:date>2014-08-27T23:34:02Z</dc:date>
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