topic Re: i.MX53 Low power VDDA in i.MX Processors

i.MX53 Low power VDDA

mfuzzey — Fri, 03 Apr 2015 08:25:13 GMT

Hello,

I am having problems understanding what should be done with VDDA on i.MX535 for low power state.

The referernce manual 9.5 says:

"All the memories' array supply (VDDA/VDDAL1) and VDD_STATE are connected to a

dedicated supply pin on i.MX53 this is done due to the fact that the memories array

supply does not support a voltage lower then 1.08V. So during DVFS the periphery

supply is lowered along with the rest of the chip."

However the recommended value in stop mode given in AN4604 "Interfacing the MC34709 with the i.MX53" is 0.95V

Furthermore the reference manual also says

"The dedicated array supply needs to be lowered to support a

maximal difference between VDDA/VDDAL1 and VDD of

300mV."

It is not clear what supply is meant by VDD. I presume this refers to the i.MX53 peripheral supply (VCC)?

When VDDA is not supplied by the PMIC but via the i.MX53 internal 1.2V LDO (VDD_DIG_PLL) (as recommended in AN4604) the voltage reduction of the VDDA has to be done by software *before* stop mode is entered and the PMIC reduces VDDC. This means that, for a short time:

VDDA = 0.95

VCC = 1.3

Hence difference = 350mV > 300mV

Also, is it OK to reduce VDDA to 0.95V while the processor is still running?

Unless, VDDA is connected to a dedicated PMIC supply there doesn't seem to be an alternative...

Regards,

Martin

Re: i.MX53 Low power VDDA

Yuri — Tue, 07 Apr 2015 06:49:39 GMT

Please use the recent i.MX53 Datasheet(s) regarding hardware specs.

In particular :

VDDA - Memory arrays voltage – should be in range 1.25 - 1.35 V under normal

operation, and it should be in range 0.9 - 1.35 V is STOP mode.
The same statement takes place for VDDAL1 (L1 Cache Memory
arrays voltage). There are no other restrictions.

Have a great day,
Yuri

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Re: i.MX53 Low power VDDA

mfuzzey — Tue, 07 Apr 2015 09:02:08 GMT

Thank you for this information.

So this means that it is not possible to reduce VDDA below 1.25V whilst respecting the constraints if VDDA is supplied from the internal LDO (as suggested in AN4604) because we have to program the i.MX53 IOMUXC GPR1 by software *before* entering STOP mode.

If a dedicated supply from the PMIC is used then this does not apply since the voltage can be reduced by hardware handshake with the PMIC *after* entering stop mode.

Regards,

Martin

Re: i.MX53 Low power VDDA

Yuri — Wed, 08 Apr 2015 05:32:03 GMT

Yes, an external PMIC is required for STOP mode.

Regards,

Yuri.