DDR3 Write Leveling

tony_l_cai — Thu, 02 Apr 2015 11:32:18 GMT

Dear All，

What the conditions will we use the DDR3 Write Leveling features？we dont know why we need to fix the following Data pin ,in other word, D0 is connected to DRAM_D8 not DRAM_D0.

FSL review command as below:

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The review was finished. One comment about DDR3 data swapping of the review,

Hardware write leveling – lowest order bit within byte lane must remain on lowest order bit of lane

by JEDEC compliance (see the “Write Leveling” section in JESD79-3E)

— D0, D8, D16, D24, D32, D40, D48, and D56 are fixed

— Other data lines free to swap within byte lane

For example, DQ0 of U3 should connect to net-label DRAM_D8.

Re: DDR3 Write Leveling

Yuri — Thu, 02 Apr 2015 11:51:52 GMT

Please look at section 11 (Write Leveling) of app note AN4467.

"i.MX 6 Series DDR Calibration"

http://cache.freescale.com/files/32bit/doc/app_note/AN4467.pdf

Have a great day,
Yuri

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i.MX Processors中的主题 DDR3 Write Leveling

DDR3 Write Leveling

Re: DDR3 Write Leveling