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    <title>i.MX Processors中的主题 i.MX6 V4L2 enqueue and dequeue timing.</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-V4L2-enqueue-and-dequeue-timing/m-p/372499#M53262</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi community,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Our partner have a question about i.MX6S V4L2 driver of L3.0.35_4.1.0 BSP.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;They understand the timing that V4L2 driver receive data as following.&lt;/P&gt;&lt;P&gt;=====&lt;/P&gt;&lt;P&gt;A buffer which is enqueued to driver by VIDIOC_QBUF have two status.&lt;/P&gt;&lt;P&gt;These are V4L2_BUF_FLAG_QUEUED and V4L2_BUF_FLAG_DONE.&lt;/P&gt;&lt;P&gt;And it will be able to be dequeued (be able to write a next data to input buffer which was enqueued in previous step) when V4L2_BUF_FLAG_DONE sutatus.&lt;/P&gt;&lt;P&gt;=====&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;However, according to the source code (comment around line 743 in drivers/media/video/mxc/output/mxc_vout.c), the first buffer can be dequeued after 3 buffers is enqueued if input buffer size = output buffer size.&lt;/P&gt;&lt;P&gt;In this case, can our partner check whether the next data can be written to the first buffer before the 3rd buffer is enqueued?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Satoshi Shimoda&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 26 Nov 2014 10:34:57 GMT</pubDate>
    <dc:creator>satoshishimoda</dc:creator>
    <dc:date>2014-11-26T10:34:57Z</dc:date>
    <item>
      <title>i.MX6 V4L2 enqueue and dequeue timing.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-V4L2-enqueue-and-dequeue-timing/m-p/372499#M53262</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi community,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Our partner have a question about i.MX6S V4L2 driver of L3.0.35_4.1.0 BSP.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;They understand the timing that V4L2 driver receive data as following.&lt;/P&gt;&lt;P&gt;=====&lt;/P&gt;&lt;P&gt;A buffer which is enqueued to driver by VIDIOC_QBUF have two status.&lt;/P&gt;&lt;P&gt;These are V4L2_BUF_FLAG_QUEUED and V4L2_BUF_FLAG_DONE.&lt;/P&gt;&lt;P&gt;And it will be able to be dequeued (be able to write a next data to input buffer which was enqueued in previous step) when V4L2_BUF_FLAG_DONE sutatus.&lt;/P&gt;&lt;P&gt;=====&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;However, according to the source code (comment around line 743 in drivers/media/video/mxc/output/mxc_vout.c), the first buffer can be dequeued after 3 buffers is enqueued if input buffer size = output buffer size.&lt;/P&gt;&lt;P&gt;In this case, can our partner check whether the next data can be written to the first buffer before the 3rd buffer is enqueued?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Satoshi Shimoda&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Nov 2014 10:34:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-V4L2-enqueue-and-dequeue-timing/m-p/372499#M53262</guid>
      <dc:creator>satoshishimoda</dc:creator>
      <dc:date>2014-11-26T10:34:57Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 V4L2 enqueue and dequeue timing.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-V4L2-enqueue-and-dequeue-timing/m-p/372500#M53263</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Satoshi-san&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Never try it but If you check the V4L2_BUF_FLAG_PREPARED in user space, The buffer has been prepared for I/O and can be queued by the application. Drivers set or clear this flag when the VIDIOC_QUERYBUF, VIDIOC_PREPARE_BUF, VIDIOC_QBUF or VIDIOC_DQBUF ioctl is called. I do not see any other way to do what your costumer is trying to do.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hope this helps&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 02 Dec 2014 17:19:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-V4L2-enqueue-and-dequeue-timing/m-p/372500#M53263</guid>
      <dc:creator>Bio_TICFSL</dc:creator>
      <dc:date>2014-12-02T17:19:12Z</dc:date>
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