Using iMX6 Solo and DDR3 - are both diff clock pairs DRAM_SDCLK_0 and DRAM_SDCLK_1 active in the Solo part?

psayles — Wed, 01 Apr 2015 14:41:46 GMT

Re: Using iMX6 Solo and DDR3 - are both diff clock pairs DRAM_SDCLK_0 and DRAM_SDCLK_1 active in the Solo part?

Yuri — Thu, 02 Apr 2015 05:31:43 GMT

Generally signals CS0, ODT0, SDCKE0 relate to the CS0 channel ; signals CS1,

ODT1, SDCKE1 relate to the CS1 channel.

Clock signals SDCLK0 and SDCLK1 in default state are the same and can be used

for both CS0 or CS1 channels if this makes easier PCB design.

Have a great day,
Yuri

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topic Re: Using iMX6 Solo and DDR3 - are both diff clock pairs DRAM_SDCLK_0 and DRAM_SDCLK_1 active in the Solo part? in i.MX Processors

Using iMX6 Solo and DDR3 - are both diff clock pairs DRAM_SDCLK_0 and DRAM_SDCLK_1 active in the Solo part?

Re: Using iMX6 Solo and DDR3 - are both diff clock pairs DRAM_SDCLK_0 and DRAM_SDCLK_1 active in the Solo part?