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    <title>topic Capacitor for MMPF0100 VINREFDDR pin. in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Capacitor-for-MMPF0100-VINREFDDR-pin/m-p/369042#M52628</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi community,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Our partner have a question about MMPF0100 connection.&lt;/P&gt;&lt;P&gt;Pelase see Table 4 of MMPF0100 datasheet (Rev.9.0).&lt;/P&gt;&lt;P&gt;It explains about VINREFDDR as following.&lt;/P&gt;&lt;P&gt;=====&lt;/P&gt;&lt;P&gt;VREFDDR regulator input. Bypass with at least 1.0 uF decoupling &lt;/P&gt;&lt;P&gt;capacitor as close to the pin as possible.&lt;/P&gt;&lt;P&gt;=====&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;However, in MCIMX6DQ-SDP schematics (SPF-27392_C3.pdf), the capacitance for VINREFDDR is less than 1.0 uF since two 0.1 uF capacitors are connected in series.&lt;/P&gt;&lt;P&gt;And 1.0 uF is connected to VREFDDR instead of VINREFDDR.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Which is correct?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Satoshi Shimoda&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 25 Nov 2014 13:09:53 GMT</pubDate>
    <dc:creator>satoshishimoda</dc:creator>
    <dc:date>2014-11-25T13:09:53Z</dc:date>
    <item>
      <title>Capacitor for MMPF0100 VINREFDDR pin.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Capacitor-for-MMPF0100-VINREFDDR-pin/m-p/369042#M52628</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi community,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Our partner have a question about MMPF0100 connection.&lt;/P&gt;&lt;P&gt;Pelase see Table 4 of MMPF0100 datasheet (Rev.9.0).&lt;/P&gt;&lt;P&gt;It explains about VINREFDDR as following.&lt;/P&gt;&lt;P&gt;=====&lt;/P&gt;&lt;P&gt;VREFDDR regulator input. Bypass with at least 1.0 uF decoupling &lt;/P&gt;&lt;P&gt;capacitor as close to the pin as possible.&lt;/P&gt;&lt;P&gt;=====&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;However, in MCIMX6DQ-SDP schematics (SPF-27392_C3.pdf), the capacitance for VINREFDDR is less than 1.0 uF since two 0.1 uF capacitors are connected in series.&lt;/P&gt;&lt;P&gt;And 1.0 uF is connected to VREFDDR instead of VINREFDDR.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Which is correct?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Satoshi Shimoda&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 25 Nov 2014 13:09:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Capacitor-for-MMPF0100-VINREFDDR-pin/m-p/369042#M52628</guid>
      <dc:creator>satoshishimoda</dc:creator>
      <dc:date>2014-11-25T13:09:53Z</dc:date>
    </item>
    <item>
      <title>Re: Capacitor for MMPF0100 VINREFDDR pin.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Capacitor-for-MMPF0100-VINREFDDR-pin/m-p/369043#M52629</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Satoshi&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;necessary capacitance is provided from DDR_1V5 side (connected to&lt;/P&gt;&lt;P&gt;VINREFDDR on SPF-27392 p.19). Also from &lt;A href="http://cache.freescale.com/files/analog/doc/data_sheet/MMPF0100.pdf?fasp=1&amp;amp;WT_TYPE=Data%20Sheets&amp;amp;WT_VENDOR=FREESCALE&amp;amp;WT_FILE_FORMAT=pdf&amp;amp;WT_ASSET=Documentation&amp;amp;fileExt=.pdf"&gt;MMPF0100&lt;/A&gt;&amp;nbsp; p.26 :&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Table 20. VREFDDR External Components..&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;VREFDDR&amp;nbsp; -- 1.0uF&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;footnote 30&lt;/P&gt;&lt;P&gt;VINREFDDR to GND, 1.0 uF minimum capacitance is provided by buck regulator output.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 25 Nov 2014 15:41:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Capacitor-for-MMPF0100-VINREFDDR-pin/m-p/369043#M52629</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2014-11-25T15:41:36Z</dc:date>
    </item>
    <item>
      <title>Re: Capacitor for MMPF0100 VINREFDDR pin.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Capacitor-for-MMPF0100-VINREFDDR-pin/m-p/369044#M52630</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for your reply.&lt;/P&gt;&lt;P&gt;OK, I understood the 1.0 uF to VREFDDR is OK.&lt;/P&gt;&lt;P&gt;And according to your reply, I understood the 1.0 uF capacitance written in footnote 30 is provided by C566, C571, C577, and C560 in &lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;SPF-27392.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;Is this correct?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Satoshi Shimoda&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Nov 2014 00:42:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Capacitor-for-MMPF0100-VINREFDDR-pin/m-p/369044#M52630</guid>
      <dc:creator>satoshishimoda</dc:creator>
      <dc:date>2014-11-26T00:42:20Z</dc:date>
    </item>
    <item>
      <title>Re: Capacitor for MMPF0100 VINREFDDR pin.</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Capacitor-for-MMPF0100-VINREFDDR-pin/m-p/369045#M52631</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Satoshi&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes, correct.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Nov 2014 13:14:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Capacitor-for-MMPF0100-VINREFDDR-pin/m-p/369045#M52631</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2014-11-26T13:14:38Z</dc:date>
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