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    <title>i.MX Processors中的主题 Re: iMX6S ADMA interrupt - timeout</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX6S-ADMA-interrupt-timeout/m-p/368813#M52558</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; Please try to apply the workaround for the next item from the Errata :&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;ERR004364 uSDHC: Limitations on uSDHC3 and uSDHC4 clock-gating&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Workarounds:&lt;/P&gt;&lt;P&gt;uSDHC3 and uSDHC4 clock-gating controls should not be configured to gate the clocks in case&lt;/P&gt;&lt;P&gt;RAWNAND and APBADMA are used. There are two registers in CCM that need to be configured&lt;/P&gt;&lt;P&gt;accordingly:&lt;/P&gt;&lt;P&gt;• CCGR: Gating of the clock according to power mode&lt;/P&gt;&lt;P&gt;• CMEOR: Enable/Disable dynamic clock gating&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf?fasp=1" title="http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf?fasp=1"&gt;http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 08 Dec 2014 11:40:12 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2014-12-08T11:40:12Z</dc:date>
    <item>
      <title>iMX6S ADMA interrupt - timeout</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6S-ADMA-interrupt-timeout/m-p/368812#M52557</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I managed to configure the ADMA2 of the iMX6S uSDHC module. I can read and write the SD card with it. However, the DMA interrupt is never set (DINT in&amp;nbsp; uSDHC_INT_STATUS) while the Transfer COmplete bit is set.&lt;/P&gt;&lt;P&gt;Here is a dump of the registers after a successfull read operation:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;=======================uSDHC0 dump===================&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;DS_ADDR:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x1459be00&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;BLK_ATT:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x00000200&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;CMD_ARG:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x07400000&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;CMD_XFR_TYP:&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x123a0000&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;CMD_RSP0:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x00000900&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;CMD_RSP1:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0xb9edb7ff&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;CMD_RSP2:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x325b5983&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;CMD_RSP3:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x00000b00&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;DATA_BUFF_ACC_PORT: 0x00000000&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;PRES_STATE:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0xff8d8088&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;PROT_CTRL:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x00800222&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;SYS_CTRL:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x008e013f&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;&lt;STRONG&gt;INT_STATUS:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x00000003&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;&lt;STRONG&gt;INT_STATUS_EN:&amp;nbsp;&amp;nbsp; 0x157f513f&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;&lt;STRONG&gt;INT_SIGNAL_EN:&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x1070000a&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;AUTOCMD12_ERR_STATUS: 0x00000000&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;HOST_CTRL_CAP:&amp;nbsp; 0x07f30000&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;WTMK_LVL:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x08000880&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;MIX_CTRL:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x00000037&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;FORCE_EVENT:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x00000000&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;ADMA_ERR_STATUS: 0x00000000&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;ADMA_SYS_ADDR:&amp;nbsp; 0x153dd008&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;DLL_CTRL:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x00000000&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;DLL_STATUS:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x00000200&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;CLK_TUNE_CTRL_STATUS: 0x00000000&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;VEND_SPEC:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x20007809&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;MMC_BOOT:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x00000000&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'andale mono', times;"&gt;VEND_SPEC2:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x00000006&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;As you can see, the TC bit and the CC bit are set, but the DINT is not. However every IT bits are set in the STATUS_EN register. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Does someone know where I am going wrong?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you i advance,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 25 Nov 2014 10:38:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6S-ADMA-interrupt-timeout/m-p/368812#M52557</guid>
      <dc:creator>philippeleduc</dc:creator>
      <dc:date>2014-11-25T10:38:52Z</dc:date>
    </item>
    <item>
      <title>Re: iMX6S ADMA interrupt - timeout</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6S-ADMA-interrupt-timeout/m-p/368813#M52558</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; Please try to apply the workaround for the next item from the Errata :&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;ERR004364 uSDHC: Limitations on uSDHC3 and uSDHC4 clock-gating&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Workarounds:&lt;/P&gt;&lt;P&gt;uSDHC3 and uSDHC4 clock-gating controls should not be configured to gate the clocks in case&lt;/P&gt;&lt;P&gt;RAWNAND and APBADMA are used. There are two registers in CCM that need to be configured&lt;/P&gt;&lt;P&gt;accordingly:&lt;/P&gt;&lt;P&gt;• CCGR: Gating of the clock according to power mode&lt;/P&gt;&lt;P&gt;• CMEOR: Enable/Disable dynamic clock gating&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf?fasp=1" title="http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf?fasp=1"&gt;http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 08 Dec 2014 11:40:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6S-ADMA-interrupt-timeout/m-p/368813#M52558</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2014-12-08T11:40:12Z</dc:date>
    </item>
    <item>
      <title>Re: iMX6S ADMA interrupt - timeout</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6S-ADMA-interrupt-timeout/m-p/368814#M52559</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I finally identified the problem of the ADMA setup: there was a bug in the cache management function --&amp;gt; the BD structure was not flushes correctly. I have also check the &lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; font-size: 12.222222328186035px; background-color: #f6f6f6;"&gt;ERR004364 but it seems that there is not concerns with it (thank you anyway Yuri :smileyhappy:).&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 02 Jan 2015 07:08:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6S-ADMA-interrupt-timeout/m-p/368814#M52559</guid>
      <dc:creator>philippeleduc</dc:creator>
      <dc:date>2015-01-02T07:08:55Z</dc:date>
    </item>
    <item>
      <title>Re: iMX6S ADMA interrupt - timeout</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6S-ADMA-interrupt-timeout/m-p/368815#M52560</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Which OS are you using? Care to share the fix?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 02 Jan 2015 13:28:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6S-ADMA-interrupt-timeout/m-p/368815#M52560</guid>
      <dc:creator>fabio_estevam</dc:creator>
      <dc:date>2015-01-02T13:28:09Z</dc:date>
    </item>
    <item>
      <title>Re: iMX6S ADMA interrupt - timeout</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6S-ADMA-interrupt-timeout/m-p/368816#M52561</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Well, it is a proprietary RTOS so I am not allowed to share this fix (which shouldn't be meaningful for another OS).&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 02 Jan 2015 13:38:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6S-ADMA-interrupt-timeout/m-p/368816#M52561</guid>
      <dc:creator>philippeleduc</dc:creator>
      <dc:date>2015-01-02T13:38:42Z</dc:date>
    </item>
    <item>
      <title>Re: iMX6S ADMA interrupt - timeout</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6S-ADMA-interrupt-timeout/m-p/368817#M52562</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Ok, got it.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 02 Jan 2015 13:51:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6S-ADMA-interrupt-timeout/m-p/368817#M52562</guid>
      <dc:creator>fabio_estevam</dc:creator>
      <dc:date>2015-01-02T13:51:30Z</dc:date>
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